SLLA581 April   2022 TCAN1462-Q1 , TCAN1463-Q1

 

  1.   Trademarks
  2. 1What is SIC?
  3. 2The Limitations of Classical CAN and Regular CAN-FD
  4. 3How CAN SIC Reduces Bus Ringing
  5. 4Experimental Results on TI’s TCAN1462 Device
  6. 5TI’s CAN SIC Devices
  7. 6Benefits of CAN SIC

1 What is SIC?

Signal improvement is an additional capability added to CAN-FD transceivers that enhances the maximum data rate achievable in complex star topologies by minimizing signal ringing. CAN SIC transceivers need to meet or exceed the specifications of the International Organization for Standardization (ISO) 11898-2:2016 high-speed CAN physical layer standard and the CAN-in-Automation (CiA) 601-4 signal improvement specification.

Figure 1-1 shows a regular CAN-FD transceiver where the CAN bus signal rings above 900 mV (the dominant threshold of a CAN receiver) and below 500 mV (the recessive threshold of a CAN receiver), resulting in receive data (RXD) glitches. With reference to CiA 601-4, Figure 1-2 shows how a CAN SIC capability transceiver attenuates bus signal ringing, resulting in the correct RXD signal.

Figure 1-1 CAN Bus and RXD Waveforms Without SIC
Figure 1-2 CAN Bus and RXD Waveforms With SIC

In terms of electrical parameters, a CiA 601-4-compliant CAN SIC transceiver has a much tighter bit-timing symmetry and loop-delay specification compared to a regular CAN-FD transceiver, as shown in Table 1-1. The segregation of delays of transmit and receive paths can help system designers clearly calculate network propagation delay in the presence of other signal chain components. One thing to note is that the timing specified in CiA 601-4 is data rate-agnostic and holds true for both 2- and 5-Mbps operation.

Table 1-1 Comparing the CiA 601-4 and ISO 11898-2 Timing Specifications
CiA 601-4 Specifications ISO 11898-2:2016 Specifications
Parameter Notation Min
[ns]		 Max
[ns]		 Min
[ns]		 Max
[ns]
Signal improvement time TX-based tSIC_TX_base N/A 530 N/A
Transmitted bit -width variation ΔtBit(Bus) –10 10 –65 for 2 Mbps 30 for 2 Mbps
–45 for 5 Mbps 10 for 5 Mbps
Received bit width ΔtBit(RxD) –30 20 –100 for 2 Mbps 50 for 2 Mbps
–80 for 5 Mbps 20 for 5 Mbps
Receiver timing symmetry ΔtREC –20 15 –65 for 2 Mbps 40 for 2 Mbps
–45 for 5 Mbps 15 for 5 Mbps
Propagation delay from transmitter data (TXD) to bus dominant tprop(TxD-busdom) 80 Only loop delay, TXD to bus to RXD, is specified at 255 ns max
Propagation delay from TXD to bus recessive tprop(TxD-busrec) 80
Propagation delay from bus to RXD dominant tprop(busdom-RxD) 110
Propagation delay from bus to RXD recessive tprop(busrec-RxD) 110