SLLSFB6B May   2020  – May 2024 DRV8705-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Descriptions
  5.   Device Comparison Table
  6. 4 Pin Configuration
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 External Components
      2. 6.3.2 Device Interface Variants
        1. 6.3.2.1 Serial Peripheral Interface (SPI)
        2. 6.3.2.2 Hardware (H/W)
      3. 6.3.3 Input PWM Modes
        1. 6.3.3.1 Half-Bridge Control
        2. 6.3.3.2 H-Bridge Control
        3. 6.3.3.3 Split HS and LS Solenoid Control
      4. 6.3.4 Smart Gate Driver
        1. 6.3.4.1 Functional Block Diagram
        2. 6.3.4.2 Slew Rate Control (IDRIVE)
        3. 6.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 6.3.5 Doubler (Single-Stage) Charge Pump
      6. 6.3.6 Low-Side Differential Current Shunt Amplifier
      7. 6.3.7 Pin Diagrams
        1. 6.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 6.3.7.2 Logic Level Push Pull Output (SDO)
        3. 6.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 6.3.7.4 Quad-Level Input (GAIN)
        5. 6.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 6.3.8 Protection and Diagnostics
        1. 6.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 6.3.8.2  Fault Reset (CLR_FLT)
        3. 6.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 6.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 6.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 6.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 6.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 6.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 6.3.8.9  Thermal Warning (OTW)
        10. 6.3.8.10 Thermal Shutdown (OTSD)
        11. 6.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 6.3.8.12 Fault Detection and Response Summary Table
    4. 6.4 Device Function Modes
      1. 6.4.1 Inactive or Sleep State
      2. 6.4.2 Standby State
      3. 6.4.3 Operating State
    5. 6.5 Programming
      1. 6.5.1 SPI Interface
      2. 6.5.2 SPI Format
      3. 6.5.3 SPI Interface for Multiple Slaves
        1. 6.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
  9. 7 Register Maps
    1. 7.1 STATUS Registers
    2. 7.2 CONTROL Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
  11. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  14. 12Revision History
  15. 13Mechanical, Packaging, and Orderable Information

Abstract

DEVICEHALF-BRIDGESAMPLIFIERSINTERFACE
DRV8705S-Q121Serial (SPI)
DRV8705H-Q12Hardware (H/W)
Table 4-1 SPI vs. H/W Feature Comparison
FeatureSPI (S) InterfaceH/W (H) Interface
PWM Input Mode 4 Modes 4 Modes
Gate Drive Output Current (IDRIVE)16 Settings, HS & LS Independent6 Settings, HS & LS Linked
Dead TimeHandshake + 7 Fixed SettingsHandshake Only
VDS Comparator Threshold16 Settings, HS & LS Independent6 Settings, HS & LS Linked
VDS and VGS Blanking Time (tDRIVE)4 SettingsFixed, 4 µs
VDS Deglitch Time4 SettingsFixed, 4 µs
VGS Deglitch TimeFixed, 2 µsFixed, 2 µs
VDS Fault Response4 ModesFixed, Cycle-By-Cycle
VGS Fault Response4 ModesFixed, Cycle-By-Cycle
Amplifier Gain4 Settings4 Settings
Amplifier Blanking Time8 SettingsN/A
Amplifier Sample and HoldAvailableN/A
Amplifier Reference Voltage2 SettingsFixed, VAREF / 2
VPVDD Undervoltage Fault Response2 ModesAuto Retry
VPVDD Overvoltage Fault Response4 ModesN/A
VVCP Undervoltage Fault Response2 ModesAuto Retry
VVCP Undervoltage Threshold2 SettingsFixed, 2.5 V
Offline Open Load DiagnosticAvailableN/A
Offline Short Circuit DiagnosticAvailableN/A