SLLSFF2B February   2022  – October 2024 TCAN1462-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configurations and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC Transients
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Characteristics
    6. 6.6  Supply Characteristics
    7. 6.7  Dissipation Ratings
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Signal Improvement
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Description
        1. 8.3.1.1 TXD
        2. 8.3.1.2 GND
        3. 8.3.1.3 VCC
        4. 8.3.1.4 RXD
        5. 8.3.1.5 VIO (only for TCAN1462V-Q1)
        6. 8.3.1.6 CANH and CANL
        7. 8.3.1.7 STB (Standby)
      2. 8.3.2 CAN Bus States
      3. 8.3.3 TXD Dominant Timeout (DTO)
      4. 8.3.4 CAN Bus Short-circuit Current Limiting
      5. 8.3.5 Thermal Shutdown (TSD)
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Unpowered Device
      8. 8.3.8 Floating pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
        1. 8.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 8.4.4 Driver and Receiver Function
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 CAN Termination
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 Bus Loading, Length and Number of Nodes
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.9 Switching Characteristics

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Device Switching Characteristics
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant See Figure 7-4 , normal mode, VIO = 4.5 V to 5.5 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF    95 145 ns
See Figure 7-4 , normal mode, VIO = 3 V to 3.6 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF    100 155 ns
See Figure 7-4 , normal mode, VIO = 2.25 V to 2.75 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF    105 170 ns
See Figure 7-4 , normal mode, VIO = 1.71 V to 1.89 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF    120 190 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive See Figure 7-4 , normal mode, VIO = 4.5 V to 5.5 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF    110 150 ns
See Figure 7-4 , normal mode, VIO = 3 V to 3.6 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF    115 160 ns
See Figure 7-4 , normal mode, VIO = 2.25 V to 2.75 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF    120 175 ns
See Figure 7-4 , normal mode, VIO = 1.71 V to 1.89 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF    135 190 ns
tMODE Mode change time, from normal to standby or from standby to normal See Figure 7-5
 		 30 µs
tWK_FILTER Filter time for a valid wake-up pattern See Figure 8-7  0.5 1.8 µs
tWK_TIMEOUT Bus wake-up timeout value See Figure 8-7  0.8 6 ms
Tstartup Time duration after VCC or VIO hass cleared rising undervoltage threshold, and device can resume normal operation 1.5 ms
Tfilter(STB) Filter on STB pin to filter out any glitches 0.5 1 2 µs
Driver Switching Characteristics
tprop(TxD-busrec) Propagation delay time, low-to-high TXD edge to driver recessive (dominant to recessive) See Figure 7-2 , STB = 0 V, RL = 60 Ω, CL = 100 pF, VIO = 4.5 V to 5.5 V 50 70 ns
See Figure 7-2 STB = 0 V, RL = 60 Ω, CL = 100 pF, VIO = 3 V to 3.6 V 50 70 ns
See Figure 7-2 STB = 0 V, RL = 60 Ω, CL = 100 pF, VIO = 2.25 V to 2.75 V 55 75 ns
See Figure 7-2 STB = 0 V, RL = 60 Ω, CL = 100 pF, VIO = 1.71 V to 1.89 V 55 80 ns
tprop(TxD-busdom) Propagation delay time, high-to-low TXD edge to driver dominant (recessive to dominant) See Figure 7-2 , STB = 0 V, RL = 60 Ω, CL = 100 pF, VIO = 4.5 V to 5.5 V 45 75 ns
See Figure 7-2 STB = 0 V, RL = 60 Ω, CL = 100 pF, VIO = 3 V to 3.6 V 50 75 ns
See Figure 7-2 STB = 0 V, RL = 60 Ω, CL = 100 pF, VIO = 2.25 V to 2.75 V 50 80 ns
See Figure 7-2 STB = 0 V, RL = 60 Ω, CL = 100 pF, VIO = 1.71 V to 1.89 V 55 80 ns
tsk(p) Pulse skew (|tprop(TxD-busrec) - tprop(TxD-busdom)|)  STB = 0 V, RL = 60 Ω, CL = 100 pF, See Figure 7-2 3.5 10 ns
tR Differential output signal rise time See Figure 7-2  , STB = 0 V, RL = 60 Ω, CL = 100 pF 20 30 ns
tF Differential output signal fall time See Figure 7-2 , STB = 0 V, RL = 60 Ω, CL = 100 pF 30 40 ns
tTXD_DTO Dominant timeout See Figure 7-6 , RL = 60 Ω, CL = 100 pF, STB = 0 V 1.2 4.0 ms
Receiver Switching Characteristics
tprop(busrec-RXD) Propagation delay time, bus recessive input to RXD high output (dominant to recessive) See Figure 7-3 , STB = 0 V,
CL(RXD) = 15 pF, VIO = 4.5 V to 5.5 V		 60 85 ns
See Figure 7-3 STB = 0 V, CL(RXD) = 15 pF, VIO = 3 V to 3.6 V 65 95 ns
See Figure 7-3 STB = 0 V, CL(RXD) = 15 pF, VIO = 2.25 V to 2.75 V 70 105 ns
See Figure 7-3 STB = 0 V, CL(RXD) = 15 pF, VIO = 1.71 V to 1.89 V 80 110 ns
tprop(busdom-RXD) Propagation delay time, bus dominant input to RXD low output (recessive to dominant) See Figure 7-3 , STB = 0 V,
CL(RXD) = 15 pF, VIO = 4.5 V to 5.5 V		 50 75 ns
See Figure 7-3 STB = 0 V, CL(RXD) = 15 pF, VIO = 3 V to 3.6 V 50 80 ns
See Figure 7-3 STB = 0 V, CL(RXD) = 15 pF, VIO = 2.25 V to 2.75 V 55 90 ns
See Figure 7-3 STB = 0 V, CL(RXD) = 15 pF, VIO = 1.71 V to 1.89 V 65 110 ns
tR RXD output signal rise time See Figure 7-3 , STB = 0 V,
CL(RXD) = 15 pF		 8 20 ns
tF RXD output signal fall time 7 25 ns
Signal Improvement Timing Characteristics
tSIC_TX_base Signal improvement time TX-based Time from rising edge of the TXD signal to the end of the signal improvement phase  230 340 530 ns
ΔtBit(Bus) Transmitted bit width variation TXD <= 5Mbps square wave, ΔtBit(Bus) = tBit(Bus) - tBit(TxD)
STB = 0 V, RL = 60 Ω, CL = 100 pF, See Figure 7-4		 –10 10 ns
ΔtBIT(RxD) Received bit width variation TXD <= 5Mbps square wave, ΔtBit(RxD) = tBit(RxD) - tBit(TxD)
STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF, See Figure 7-4		 –30 20 ns
ΔtREC Receiver timing symmetry TXD <= 5Mbps square wave, ΔtREC = tBit(RxD) - tBit(Bus)
STB = 0 V, CL(RXD) = 15 pF, See Figure 7-4		 –20 15 ns
FD Timing Characteristics
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns See Figure 7-4 , STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
 		 490 510 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns 190 210 ns
Bit time on CAN bus output pins with tBIT(TXD) = 125 ns(1) 115 135 ns
tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns 470 520 ns
Bit time on RXD output pins with tBIT(TXD) = 200 ns 170 220 ns
Bit time on RXD output pins with tBIT(TXD) = 125 ns(1) 95 145 ns
ΔtREC Receiver timing symmetry with tBIT(TXD) = 500 ns See Figure 7-4 , RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)		 -20 15 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns -20 15 ns
Receiver timing symmetry with tBIT(TXD) = 125 ns(1) -20 15 ns
(1) Measured during characterization and not an ISO 11898-2:2016 parameter