SLLSFP4A July   2022  – August 2026 ISOW7721

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics - Power Converter
    10. 5.10 Supply Current Characteristics - Power Converter
    11. 5.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V
    12. 5.12 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 5-V
    13. 5.13 Electrical Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
    14. 5.14 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
    15. 5.15 Electrical Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
    16. 5.16 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
    17. 5.17 Electrical Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
    18. 5.18 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
    19. 5.19 Switching Characteristics - 5-V Supply
    20. 5.20 Switching Characteristics - 3.3-V Supply
    21. 5.21 Switching Characteristics - 2.5-V Supply
    22. 5.22 Switching Characteristics - 1.8-V Supply
    23. 5.23 Insulation Characteristics Curves
    24. 5.24 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Power Isolation
      2. 7.1.2 Signal Isolation
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 7.3.2 Power-Up and Power-Down Behavior
      3. 7.3.3 Protection Features
      4. 7.3.4 Multi-Device Chaining for Increased Power Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
        1. 8.2.3.1 Insulation Lifetime
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2 Power-Up and Power-Down Behavior

The ISOW7721 has built-in UVLO on the VIO, VDD, and VISOIN supplies with positive-going and negative-going thresholds and hysteresis. Both the power converter supply (VDD) and logic supply (VIO) need to be present for the device to work. If either of them is below UVLO, both the signal path and the power converter are disabled.

When the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner, avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VIO and VDD voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the secondary side VISOOUT pin, the feedback data channel starts providing feedback to the primary controller. The regulation loop takes over and the isolated data channels go to the normal state defined by the respective input channels or the default states. Design must consider a sufficient time margin (typically 10ms with 10µF load capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.

When either VIO or VDD power is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached. The VISOOUT capacitor then discharges depending on the external load. The isolated data outputs on the VISOIN side are returned to the default state for the brief time that the VISOIN voltage takes to discharge to zero.