SLLSFT3 November   2025 MC121-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Motor Control
        1. 6.3.1.1 Duty Input
        2. 6.3.1.2 Duty Curve
        3. 6.3.1.3 Motor Start, Speed Change, and Stop
        4. 6.3.1.4 Open-Loop (Duty Cycle) Control
        5. 6.3.1.5 Closed-Loop (Speed) Control
        6. 6.3.1.6 Commutation
          1. 6.3.1.6.1 Hall Sensor
            1. 6.3.1.6.1.1 Field Direction Definition
            2. 6.3.1.6.1.2 Internal Hall Latch Sensor Output
          2. 6.3.1.6.2 Hall Offset
          3. 6.3.1.6.3 Square Commutation
          4. 6.3.1.6.4 Soft Commutation
        7. 6.3.1.7 PWM Modulation Modes
      2. 6.3.2 Protections
        1. 6.3.2.1 Locked Rotor Protection
        2. 6.3.2.2 Current Limit
        3. 6.3.2.3 Overcurrent Protection (OCP)
        4. 6.3.2.4 VM Undervoltage Lockout (UVLO)
        5. 6.3.2.5 VM Over Voltage Protection (OVP)
        6. 6.3.2.6 Thermal Shutdown (TSD)
        7. 6.3.2.7 Integrated Supply (VM) Clamp
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Sleep and Standby Mode
      3. 6.4.3 Fault Mode
      4. 6.4.4 Test Mode and One-Time Programmable Memory
    5. 6.5 Programming
      1. 6.5.1 I2C Communication
        1. 6.5.1.1 I2C Read
        2. 6.5.1.2 I2C Write
  8. 7 Register Map
    1. 7.1 USR_OTP Registers
    2. 7.2 USR_TM Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Components
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History

7.2 USR_TM Registers

Table 7-31 lists the memory-mapped registers for the USR_TM registers. All register offset addresses not listed in Table 7-31 should be considered as reserved locations and the register contents should not be modified.

Table 7-31 USR_TM Registers
Offset Acronym Register Name Section
20h TEST_FAULT Register to test for Fault Section 7.2.1
21h TEST_DIN Input Duty Cycle Control Section 7.2.2
22h TEST_FAULT_STATUS Register to indicate Fault type Section 7.2.3
23h TEST_SPEED_MSB Speed Feedback Section 7.2.4
24h TEST_SPEED_LSB Speed Feedback Section 7.2.5
25h USR_OTP_CFG Register to configure USR_OTP Programming Section 7.2.6
26h USR_OTP_PRG_UNLOCK Unlock access to program or verify USR_OTP Section 7.2.7

Complex bit access types are encoded to fit into small table cells. Table 7-32 shows the codes that are used for access types in this section.

Table 7-32 USR_TM Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W0C W
0C		 Write
0 to clear
Reset or Default Value
-n Value after reset or the default value

7.2.1 TEST_FAULT Register (Offset = 20h) [Reset = 00h]

TEST_FAULT is shown in Table 7-33.

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Table 7-33 TEST_FAULT Register Field Descriptions
Bit Field Type Reset Description
7 FAULT R 0h Reading this bit indicates that the device is in a fault mode (OCP, OVP, UVLO, Rotor Lock, TSD). Current limiting operation does not report on this bit.
  • 0h = Active mode
  • 1h = Fault mode
6-0 RESERVED R 0h Reserved

7.2.2 TEST_DIN Register (Offset = 21h) [Reset = 01h]

TEST_DIN is shown in Table 7-34.

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Table 7-34 TEST_DIN Register Field Descriptions
Bit Field Type Reset Description
7-0 DIN_CNTRL R/W 1h Writing to this register sets the inpit duty cycle DIN to control speed while the PWM pin is not available in I2C.
DIN = DIN_CTRL/255
  • 0h = 0% (default)
  • A0h = 62.5%
  • FFh = 100%

7.2.3 TEST_FAULT_STATUS Register (Offset = 22h) [Reset = 00h]

TEST_FAULT_STATUS is shown in Table 7-35.

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Table 7-35 TEST_FAULT_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 0h Reserved
5 RESERVED R/W0C 0h Reserved
4 TSD R/W0C 0h Reading this bit indicates that the device is in temperature shutdown (TSD) protection.
  • 0h = Normal operation
  • 1h = TSD fault
3 UVLO R 0h Reading this bit indicates that the device is in undervoltage (UVLO).
  • 0h = Normal operation
  • 1h = UVLO fault
2 OVP R/W0C 0h Reading this bit indicates that the device is in overvoltage protection (OVP).
  • 0h = Normal operation
  • 1h = OVP fault
1 LRP R 0h Reading this bit indicates that the device is in locked rotor protection (LRP).
  • 0h = Normal operation
  • 1h = LRP fault
0 OCP R/W0C 0h Reading this bit indicates that the device in overcurrent protection.
  • 0h = Normal operation
  • 1h = OCP fault

7.2.4 TEST_SPEED_MSB Register (Offset = 23h) [Reset = 00h]

TEST_SPEED_MSB is shown in Table 7-36.

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Table 7-36 TEST_SPEED_MSB Register Field Descriptions
Bit Field Type Reset Description
7-0 ELECTRICAL_PERIOD_MSB R 0h Reading this register provides the period of the motor's electrical cycle. This helps provide speed feedback during test mode since the FG pin is not available. Formula for Electrical Half Cycle Duration is 10.24us * ((ELECTRICAL_PERIOD_MSB << 8) + (ELECTRICAL_PERIOD)) Total Electrical Period would be twice the value calculated above

7.2.5 TEST_SPEED_LSB Register (Offset = 24h) [Reset = 00h]

TEST_SPEED_LSB is shown in Table 7-37.

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Table 7-37 TEST_SPEED_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 ELECTRICAL_PERIOD_LSB R 0h Reading this register provides the period of the motor's electrical cycle. This helps provide speed feedback during test mode since the FG pin is not available. Formula in ELECTRICAL_PERIOD_MSB bit field description..

7.2.6 USR_OTP_CFG Register (Offset = 25h) [Reset = 00h]

USR_OTP_CFG is shown in Table 7-38.

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Table 7-38 USR_OTP_CFG Register Field Descriptions
Bit Field Type Reset Description
7 USR_OTP_CRC_ERR R 0h Status of USR_OTP_CRC check
  • 0h = No CRC error
  • 1h = CRC err
6 DEVICE_OTP_CRC_ERR R 0h Status of DEVICE OTP CRC computed for DEVICE OTP contents
  • 0h = No CRC error
  • 1h = CRC err
5 RESERVED R/W 0h Reserved
4-3 USR_OTP_PAGE_USED R 0h Indicates the origin of the data used for any loading of USR_OTP Shadow Registers
  • 0h = Shadow Registers not loaded from either of the USR_OTPs so far. This implies that USR_OTP1 was sensed to be unprogrammed on power-up.
  • 1h = Latest load of Shadow Registers was from USR_OTP1
  • 2h = Latest load of Shadow Registers was from USR_OTP2.
  • 3h = Invalid combination which is not expected.
2 USR_OTP_PAGE_SEL R/W 0h This bit indicates whether first USR_OTP page (USR_OTP1) is targeted for commanded operation, or second USR_OTP page (USR_OTP2) is targeted.
  • 0h = USR_OTP1
  • 1h = USR_OTP2
1 USR_OTP_PROG_VERIFY R/W 0h Reserved
0 USR_OTP_PROG_ALL R/W 0h Write 1h to this bit to program the USR_OTP page according to USR_OTP_PAGE_SEL

7.2.7 USR_OTP_PRG_UNLOCK Register (Offset = 26h) [Reset = 00h]

USR_OTP_PRG_UNLOCK is shown in Table 7-39.

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Table 7-39 USR_OTP_PRG_UNLOCK Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 0h Reserved
2-0 USR_OTP_PROG_UNLOCK R 0h User needs to write a sequence of 2h,1h,4h to this bits in successive write-frames, to unlock access to USR_OTP programming or program-verify operations