SLLSFV2A August   2023  – July 2026 MCF8316C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog-Mode Motor Control
        2. 6.3.8.2 PWM-Mode Motor Control
        3. 6.3.8.3 I2C-based Motor Control
        4. 6.3.8.4 Frequency-Mode Motor Control
        5. 6.3.8.5 Input Reference Profiles
          1. 6.3.8.5.1 Linear Reference Profiles
          2. 6.3.8.5.2 Staircase Speed Profile
          3. 6.3.8.5.3 Forward-Reverse Speed Profile
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
        4. 6.3.10.4 Motor Start-up
          1. 6.3.10.4.1 Align
          2. 6.3.10.4.2 Double Align
          3. 6.3.10.4.3 Initial Position Detection (IPD)
            1. 6.3.10.4.3.1 IPD Operation
            2. 6.3.10.4.3.2 IPD Release Mode
            3. 6.3.10.4.3.3 IPD Advance Angle
          4. 6.3.10.4.4 Slow First Cycle Startup
          5. 6.3.10.4.5 Open Loop
          6. 6.3.10.4.6 Transition from Open to Closed Loop
      11. 6.3.11 Closed Loop Operation
        1. 6.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.11.2 Speed PI Control
        3. 6.3.11.3 Current PI Control
        4. 6.3.11.4 Torque Mode
        5. 6.3.11.5 Overmodulation
      12. 6.3.12 Motor Parameters
        1. 6.3.12.1 Motor Resistance
        2. 6.3.12.2 Motor Inductance
        3. 6.3.12.3 Motor Back-EMF constant
      13. 6.3.13 Motor Parameter Extraction Tool (MPET)
      14. 6.3.14 Anti-Voltage Surge (AVS)
      15. 6.3.15 Active Braking
      16. 6.3.16 Output PWM Switching Frequency
      17. 6.3.17 PWM Modulation Schemes
      18. 6.3.18 Dead Time Compensation
      19. 6.3.19 Motor Stop Options
        1. 6.3.19.1 Coast (Hi-Z) Mode
        2. 6.3.19.2 Low-Side Braking
        3. 6.3.19.3 High-Side Braking
        4. 6.3.19.4 Active Spin-Down
        5. 6.3.19.5 Align Braking
      20. 6.3.20 FG Configuration
        1. 6.3.20.1 FG Output Frequency
        2. 6.3.20.2 FG during Open and Closed Loop States
        3. 6.3.20.3 FG during Fault and Idle States
      21. 6.3.21 DC Bus Current Limit
      22. 6.3.22 Protections
        1. 6.3.22.1  VM Supply Undervoltage Lockout
        2. 6.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.22.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.22.5  Overvoltage Protection (OVP)
        6. 6.3.22.6  Overcurrent Protection (OCP)
          1. 6.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.22.7  Buck Overcurrent Protection
        8. 6.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 6.3.22.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 6.3.22.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.22.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.22.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.22.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 6.3.22.10 FET Thermal Warning (OTW)
        11. 6.3.22.11 FET Thermal Shutdown (TSD_FET)
        12. 6.3.22.12 Motor Lock (MTR_LCK)
          1. 6.3.22.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 6.3.22.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 6.3.22.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 6.3.22.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 6.3.22.13 Motor Lock Detection
          1. 6.3.22.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.22.13.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.22.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 6.3.22.14 MPET Faults
        15. 6.3.22.15 IPD Faults
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC outputs
      3. 6.5.3 Current Sense Output
      4. 6.5.4 Oscillator Source
        1. 6.5.4.1 External Clock Source
      5. 6.5.5 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
  8. 7 EEPROM (Non-Volatile) Register Map
    1. 7.1 Algorithm_Configuration Registers
    2. 7.2 Fault_Configuration Registers
    3. 7.3 Hardware_Configuration Registers
    4. 7.4 Internal_Algorithm_Configuration Registers
  9. 8 RAM (Volatile) Register Map
    1. 8.1 Fault_Status Registers
    2. 8.2 System_Status Registers
    3. 8.3 Device_Control Registers
    4. 8.4 Algorithm_Control Registers
    5. 8.5 Algorithm_Variables Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Curves
        1. 9.2.1.1 Motor startup
        2. 9.2.1.2 MPET
        3. 9.2.1.3 Dead time compensation
        4. 9.2.1.4 Auto handoff
        5. 9.2.1.5 Anti voltage surge (AVS)
        6. 9.2.1.6 Real time variable tracking using DACOUT
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
        1. 9.4.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Support Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3 Hardware_Configuration Registers

Table 7-21 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 7-21 should be considered as reserved locations and the register contents should not be modified.

Table 7-21 HARDWARE_CONFIGURATION Registers
OffsetAcronymRegister NameSection
A4hPIN_CONFIGHardware Pin ConfigurationGo
A6hDEVICE_CONFIG1Device configuration1Go
A8hDEVICE_CONFIG2Device configuration2Go
AAhPERI_CONFIG1Peripheral Configuration1Go
AChGD_CONFIG1Gate Driver Configuration1Go
AEhGD_CONFIG2Gate Driver Configuration2Go

Complex bit access types are encoded to fit into small table cells. Table 7-22 shows the codes that are used for access types in this section.

Table 7-22 Hardware_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

7.3.1 PIN_CONFIG Register (Offset = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in Figure 7-17 and described in Table 7-23.

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Register to configure hardware pins

Figure 7-17 PIN_CONFIG Register
3130292827262524
PARITYRESERVEDVDC_FILT_DISRESERVED
R/W-0hR-0hR/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDFG_IDLE_CONFIGFG_FAULT_CONFIG
R-0hR-0hR/W-0hR/W-0h
76543210
FG_FAULT_CONFIGALARM_PIN_ENRESERVEDRESERVEDBRAKE_INPUTSPEED_MODE
R/W-0hR/W-0hR-0hR-0hR/W-0hR/W-0h
Table 7-23 PIN_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-28RESERVEDR0h Reserved
27VDC_FILT_DISR/W0h Vdc (VM) filter disable
  • 0h = Vdc filter Enable
  • 1h = Vdc filter Disable
26-13RESERVEDR0h Reserved
12-11RESERVEDR0h Reserved
10-9FG_IDLE_CONFIGR/W0h FG configuration during motor stopped/idle state
  • 0h = FG continues and end state depends on FG_CONFIG and last state before motor stops
  • 1h = FG is pulled High
  • 2h = FG is pulled Low
  • 3h = FG is pulled High
8-7FG_FAULT_CONFIGR/W0h FG configuration during fault state
  • 0h = Use last FG signal when motor was driven
  • 1h = FG is pulled High
  • 2h = FG is pulled Low
6ALARM_PIN_ENR/W0h Alarm pin enable
  • 0h = Disable
  • 1h = Enable
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3-2BRAKE_INPUTR/W0h Brake pin override
  • 0h = Hardware Pin BRAKE
  • 1h = Override pin and apply low side brake
  • 2h = Override pin and do not brake/align
  • 3h = Hardware Pin BRAKE
1-0SPEED_MODER/W0h Configure motor control input source
  • 0h = Controlled by analog voltage on SPEED pin
  • 1h = Controlled by duty cycle (PWM) on SPEED pin
  • 2h = Controlled by DIGITAL_SPEED_CTRL value (I2C)
  • 3h = Controlled by frequency on SPEED pin

7.3.2 DEVICE_CONFIG1 Register (Offset = A6h) [Reset = 00000000h]

DEVICE_CONFIG1 is shown in Figure 7-18 and described in Table 7-24.

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Register to configure device

Figure 7-18 DEVICE_CONFIG1 Register
3130292827262524
PARITYRESERVEDDAC_SOx_SELDAC_ENABLEI2C_TARGET_ADDR
R/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
I2C_TARGET_ADDRRESERVED
R/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSLEW_RATE_I2C_PINSPULLUP_ENABLEBUS_VOLT
R-0hR/W-0hR/W-0hR/W-0h
Table 7-24 DEVICE_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30RESERVEDR0h Reserved
29-28DAC_SOx_SELR/W0h Selects between DAC2 and SOx channels
  • 0h = DACOUT2
  • 1h = SOA
  • 2h = SOB
  • 3h = SOC
27DAC_ENABLER/W0h DAC enable
  • 0h = DACOUT1 and DACOUT2 on dedicated DAC pins disabled
  • 1h = DACOUT1 and DACOUT2 on dedicated DAC pins enabled
26-20I2C_TARGET_ADDRR/W0h I2C target address
19-5RESERVEDR0h Reserved
4-3SLEW_RATE_I2C_PINSR/W0h Slew rate control for I2C pins
  • 0h = 4.8mA
  • 1h = 3.9mA
  • 2h = 1.86mA
  • 3h = 30.8mA
2PULLUP_ENABLER/W0h Pull-up enable for nFAULT and FG pins
  • 0h = Disable
  • 1h = Enable
1-0BUS_VOLTR/W0h Maximum DC bus voltage configuration
  • 0h = 15V
  • 1h = 30V
  • 2h = 60V
  • 3h = Not applicable

7.3.3 DEVICE_CONFIG2 Register (Offset = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in Figure 7-19 and described in Table 7-25.

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Register to configure device

Figure 7-19 DEVICE_CONFIG2 Register
3130292827262524
PARITYINPUT_MAXIMUM_FREQ
R/W-0hR/W-0h
2322212019181716
INPUT_MAXIMUM_FREQ
R/W-0h
15141312111098
SLEEP_ENTRY_TIMEDYNAMIC_CSA_GAIN_ENDYNAMIC_VOLTAGE_GAIN_ENDEV_MODECLK_SELEXT_CLK_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EXT_CLK_CONFIGEXT_WDT_ENEXT_WDT_CONFIGEXT_WDT_INPUT_MODEEXT_WDT_FAULT_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-25 DEVICE_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-16INPUT_MAXIMUM_FREQR/W0h Input frequency on SPEED pin for input reference mode as "controlled by frequency on SPEED pin" that corresponds to 100% duty cycle. Duty cycle = Input frequency / INPUT_MAXIMUM_FREQ
15-14SLEEP_ENTRY_TIMER/W0h Device enters sleep mode when input source is held at or below the sleep entry threshold for SLEEP_ENTRY_TIME
  • 0h = Sleep entry when SPEED pin remains low for 50µs
  • 1h = Sleep entry when SPEED pin remains low for 200µs
  • 2h = Sleep entry when SPEED pin remains low for 20ms
  • 3h = Sleep entry when SPEED pin remains low for 200ms
13DYNAMIC_CSA_GAIN_ENR/W0h Adjust CSA gain dynamically for optimal resolution at current levels
  • 0h = Dynamic CSA gain is disabled
  • 1h = Dynamic CSA gain is enabled
12DYNAMIC_VOLTAGE_GAIN_ENR/W0h Adjust voltage gain dynamically for optimal voltage resolution at voltage levels
  • 0h = Dynamic voltage gain is disabled
  • 1h = Dynamic voltage gain is enabled
11DEV_MODER/W0h Device mode select
  • 0h = Standby Mode
  • 1h = Sleep Mode
10-9CLK_SELR/W0h Clock source
  • 0h = Internal Oscillator
  • 1h = Not Applicable
  • 2h = Not Applicable
  • 3h = External Clock input
8EXT_CLK_ENR/W0h Enable external clock mode
  • 0h = Disable
  • 1h = Enable
7-5EXT_CLK_CONFIGR/W0h External clock configuration
  • 0h = 8kHz
  • 1h = 16kHz
  • 2h = 32kHz
  • 3h = 64kHz
  • 4h = 128kHz
  • 5h = 256kHz
  • 6h = 512kHz
  • 7h = 1024kHz
4EXT_WDT_ENR/W0h Enable external watchdog
  • 0h = Disable
  • 1h = Enable
3-2EXT_WDT_CONFIGR/W0h Time between watchdog tickles (GPIO/I2C)
  • 0h = 100ms/1s
  • 1h = 200ms/2s
  • 2h = 500ms/5s
  • 3h = 1000ms/10s
1EXT_WDT_INPUT_MODER/W0h External watchdog input mode
  • 0h = Watchdog tickle over I2C
  • 1h = Watchdog tickle over GPIO
0EXT_WDT_FAULT_MODER/W0h External watchdog fault mode
  • 0h = Report Only
  • 1h = Latch with FETs in Hi-Z

7.3.4 PERI_CONFIG1 Register (Offset = AAh) [Reset = 40000000h]

PERI_CONFIG1 is shown in Figure 7-20 and described in Table 7-26.

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Register to peripheral1

Figure 7-20 PERI_CONFIG1 Register
3130292827262524
PARITYSPREAD_SPECTRUM_MODULATION_DISRESERVEDBUS_CURRENT_LIMIT
R/W-0hR/W-1hR-0hR/W-0h
2322212019181716
BUS_CURRENT_LIMITBUS_CURRENT_LIMIT_ENABLEDIR_INPUTDIR_CHANGE_MODERESERVEDACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYACTIVE_BRAKE_MOD_INDEX_LIMITSPEED_RANGE_SELRESERVED
R/W-0hR/W-0hR/W-0hR-0h
76543210
RESERVED
R-0h
Table 7-26 PERI_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30SPREAD_SPECTRUM_MODULATION_DISR/W1h Spread Spectrum Modulation disable
  • 0h = SSM is Enabled
  • 1h = SSM is Disabled
29-26RESERVEDR0h Reserved
25-22BUS_CURRENT_LIMITR/W0h Bus current limit
  • 0h = 0.125A
  • 1h = 0.25A
  • 2h = 0.5A
  • 3h = 1.0A
  • 4h = 1.5A
  • 5h = 2.0A
  • 6h = 2.5A
  • 7h = 3.0A
  • 8h = 3.5A
  • 9h = 4.0A
  • Ah = 4.5A
  • Bh = 5.0A
  • Ch = 5.5A
  • Dh = 6.0A
  • Eh = 7.0A
  • Fh = 8.0A
21BUS_CURRENT_LIMIT_ENABLER/W0h Bus current limit enable
  • 0h = Disable
  • 1h = Enable
20-19DIR_INPUTR/W0h DIR pin override
  • 0h = Hardware Pin DIR
  • 1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC
  • 2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-OUTB
  • 3h = Hardware Pin DIR
18DIR_CHANGE_MODER/W0h Response to change of DIR pin status
  • 0h = Follow motor stop options and ISD routine on detecting DIR change
  • 1h = Change the direction through Reverse Drive while continuously driving the motor
17RESERVEDR0h Reserved
16-13ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYR/W0h Difference between final speed and present speed below which active braking will be applied
  • 0h = Not Applicable
  • 1h = 5%
  • 2h = 10%
  • 3h = 15%
  • 4h = 20%
  • 5h = 25%
  • 6h = 30%
  • 7h = 35%
  • 8h = 40%
  • 9h = 45%
  • Ah = 50%
  • Bh = 60%
  • Ch = 70%
  • Dh = 80%
  • Eh = 90%
  • Fh = 100%
12-10ACTIVE_BRAKE_MOD_INDEX_LIMITR/W0h Modulation index limit below which active braking will be applied
  • 0h = 0%
  • 1h = 40%
  • 2h = 50%
  • 3h = 60%
  • 4h = 70%
  • 5h = 80%
  • 6h = 90%
  • 7h = 100%
9SPEED_RANGE_SELR/W0h Frequency range selection for PWM duty mode reference input
  • 0h = 325Hz to 100kHz
  • 1h = 10Hz to 325Hz
8RESERVEDR0h Reserved
7-0RESERVEDR0h Reserved

7.3.5 GD_CONFIG1 Register (Offset = ACh) [Reset = 10228100h]

GD_CONFIG1 is shown in Figure 7-21 and described in Table 7-27.

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Register to configure gated driver settings1

Figure 7-21 GD_CONFIG1 Register
3130292827262524
PARITYRESERVEDRESERVEDSLEW_RATERESERVED
R/W-0hR-0hR-0hR/W-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDOVP_SELOVP_ENRESERVEDRESERVED
R-0hR-0hR-0hR-0hR/W-0hR/W-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDOCP_DEGRESERVEDOCP_LVLOCP_MODE
R-0hR-0hR/W-0hR-0hR/W-0hR/W-1h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCSA_GAIN
R-0hR-0hR-0hR-0hR-0hR-0hR/W-0h
Table 7-27 GD_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29RESERVEDR0h Reserved
28RESERVEDR0h Reserved
27-26SLEW_RATER/W0h Slew rate
  • 0h = Not Applicable
  • 1h = Not Applicable
  • 2h = Slew rate is 125V/µs
  • 3h = Slew rate is 200V/µs
25-24RESERVEDR0h Reserved
23RESERVEDR0h Reserved
22RESERVEDR0h Reserved
21RESERVEDR0h Reserved
20RESERVEDR0h Reserved
19OVP_SELR/W0h Overvoltage level
  • 0h = VM overvoltage level is 34V
  • 1h = VM overvoltage level is 22V
18OVP_ENR/W0h Overvoltage enable
  • 0h = Overvoltage protection is disabled
  • 1h = Overvoltage protection is enabled
17RESERVEDR0h Reserved
16RESERVEDR0h Reserved
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13-12OCP_DEGR/W0h OCP deglitch time
  • 0h = OCP deglitch time is 0.2µs
  • 1h = OCP deglitch time is 0.6µs
  • 2h = OCP deglitch time is 1.1µs
  • 3h = OCP deglitch time is 1.6µs
11RESERVEDR0h Reserved
10OCP_LVLR/W0h Overcurrent level
  • 0h = OCP level is 16A (Typical)
  • 1h = OCP level is 24A (Typical)
9-8OCP_MODER/W1h OCP fault mode
  • 0h = Overcurrent causes a latched fault
  • 1h = Overcurrent causes an automatic retrying fault after 500ms
  • 2h = Not Applicable
  • 3h = Not Applicable
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3RESERVEDR0h Reserved
2RESERVEDR0h Reserved
1-0CSA_GAINR/W0h Current Sense Amplifier gain (used only if DYNAMIC_CSA_GAIN_EN = 0b)
  • 0h = CSA gain is 0.15V/A
  • 1h = CSA gain is 0.3V/A
  • 2h = CSA gain is 0.6V/A
  • 3h = CSA gain is 1.2V/A

7.3.6 GD_CONFIG2 Register (Offset = AEh) [Reset = 01200000h]

GD_CONFIG2 is shown in Figure 7-22 and described in Table 7-28.

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Register to configure gated driver settings2

Figure 7-22 GD_CONFIG2 Register
3130292827262524
PARITYRESERVEDRESERVEDRESERVEDBUCK_PS_DIS
R/W-0hR-0hR-0hR-0hR/W1C-1h
2322212019181716
BUCK_CLBUCK_SELBUCK_DISMIN_ON_TIMERESERVED
R/W-0hR/W-1hR/W-0hR/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 7-28 GD_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30RESERVEDR0h Reserved
29-26RESERVEDR0h Reserved
25RESERVEDR0h Reserved
24BUCK_PS_DISR/W1C1h Buck power sequencing disable
  • 0h = Buck power sequencing is enabled
  • 1h = Buck power sequencing is disabled
23BUCK_CLR/W0h Buck current limit
  • 0h = Buck regulator current limit is set to 600mA
  • 1h = Buck regulator current limit is set to 150mA
22-21BUCK_SELR/W1h Buck voltage
  • 0h = Buck voltage is 3.3V
  • 1h = Buck voltage is 5.0V
  • 2h = Buck voltage is 4.0V
  • 3h = Buck voltage is 5.7V
20BUCK_DISR/W0h Buck disable
  • 0h = Buck regulator is enabled
  • 1h = Buck regulator is disabled
19-17MIN_ON_TIMER/W0h Minimum ON time for low side MOSFET
  • 0h = 0µs
  • 1h = Automatic based on slew rate
  • 2h = 0.5µs
  • 3h = 0.75µs
  • 4h = 1µs
  • 5h = 1.25µs
  • 6h = 1.5µs
  • 7h = 2µs
16-0RESERVEDR0h Reserved