SLLSFV6B January   2024  – September 2025 MCF8315C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
        6. 6.3.3.6 Buck Under Voltage Protection
        7. 6.3.3.7 Buck Over Current Protection
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog Mode Motor Control
        2. 6.3.8.2 PWM Mode Motor Control
        3. 6.3.8.3 I2C based Motor Control
        4. 6.3.8.4 Frequency Mode Motor Control
        5. 6.3.8.5 Speed Profiles
          1. 6.3.8.5.1 Linear Reference Profiles
          2. 6.3.8.5.2 Staircase Reference Profiles
          3. 6.3.8.5.3 Forward-Reverse Reference Profiles
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
      11. 6.3.11 Motor Start-up
        1. 6.3.11.1 Align
        2. 6.3.11.2 Double Align
        3. 6.3.11.3 Initial Position Detection (IPD)
          1. 6.3.11.3.1 IPD Operation
          2. 6.3.11.3.2 IPD Release Mode
          3. 6.3.11.3.3 IPD Advance Angle
        4. 6.3.11.4 Slow First Cycle Start-up
        5. 6.3.11.5 Open loop
        6. 6.3.11.6 Transition from Open to Closed Loop
      12. 6.3.12 Closed Loop Operation
        1. 6.3.12.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.12.2 Speed PI Control
        3. 6.3.12.3 Current PI Control
        4. 6.3.12.4 Torque Mode
        5. 6.3.12.5 Overmodulation
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 PWM Modulation Schemes
      19. 6.3.19 Dead Time Compensation
      20. 6.3.20 Motor Stop Options
        1. 6.3.20.1 Coast (Hi-Z) Mode
        2. 6.3.20.2 Low-Side Braking
        3. 6.3.20.3 Active Spin-Down
      21. 6.3.21 FG Configuration
        1. 6.3.21.1 FG Output Frequency
        2. 6.3.21.2 FG during open loop
        3. 6.3.21.3 FG during idle and fault
      22. 6.3.22 DC Bus Current Limit
      23. 6.3.23 Protections
        1. 6.3.23.1  VM Supply Undervoltage Lockout
        2. 6.3.23.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.23.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.23.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.23.5  Overvoltage Protection (OVP)
        6. 6.3.23.6  Overcurrent Protection (OCP)
          1. 6.3.23.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.23.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.23.7  Buck Overcurrent Protection
        8. 6.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 6.3.23.9  Motor Lock (MTR_LCK)
          1. 6.3.23.9.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 6.3.23.9.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 6.3.23.9.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 6.3.23.9.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        10. 6.3.23.10 Motor Lock Detection
          1. 6.3.23.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.23.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.23.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 6.3.23.11 Minimum VM (undervoltage) Protection
        12. 6.3.23.12 Maximum VM (overvoltage) Protection
        13. 6.3.23.13 MPET Faults
        14. 6.3.23.14 IPD Faults
        15. 6.3.23.15 Thermal Warning (OTW)
        16. 6.3.23.16 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC output
      3. 6.5.3 Current Sense Output
      4. 6.5.4 Oscillator Source
        1. 6.5.4.1 External Clock Source
      5. 6.5.5 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
  8. 7 EEPROM (Non-Volatile) Register Map
    1. 7.1 Algorithm_Configuration Registers
    2. 7.2 Fault_Configuration Registers
    3. 7.3 Hardware_Configuration Registers
    4. 7.4 Internal_Algorithm_Configuration Registers
  9. 8 RAM (Volatile) Register Map
    1. 8.1 Fault_Status Registers
    2. 8.2 System_Status Registers
    3. 8.3 Device_Control Registers
    4. 8.4 Algorithm_Control Registers
    5. 8.5 Algorithm_Variables Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Curves
        1. 9.2.1.1 Motor startup
        2. 9.2.1.2 MPET
        3. 9.2.1.3 Dead time compensation
        4. 9.2.1.4 Auto handoff
        5. 9.2.1.5 Anti voltage surge (AVS)
        6. 9.2.1.6 Real time variable tracking using DACOUT
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Thermal Considerations
        1. 9.4.2.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.5 Algorithm_Variables Registers

Table 8-21 lists the memory-mapped registers for the Algorithm_Variables registers. All register offset addresses not listed in Table 8-21 should be considered as reserved locations and the register contents should not be modified.

Table 8-21 ALGORITHM_VARIABLES Registers
OffsetAcronymRegister NameSection
190hALGORITHM_STATECurrent Algorithm State RegisterSection 8.5.1
196hFG_SPEED_FDBKFG Speed Feedback RegisterSection 8.5.2
410hBUS_CURRENTCalculated DC Bus Current RegisterSection 8.5.3
440hPHASE_CURRENT_AMeasured Current on Phase A RegisterSection 8.5.4
442hPHASE_CURRENT_BMeasured Current on Phase B RegisterSection 8.5.5
444hPHASE_CURRENT_CMeasured Current on Phase C RegisterSection 8.5.6
468hCSA_GAIN_FEEDBACKCSA Gain RegisterSection 8.5.7
472hVOLTAGE_GAIN_FEEDBACKVoltage Gain RegisterSection 8.5.8
474hVM_VOLTAGEVM Voltage RegisterSection 8.5.9
47AhPHASE_VOLTAGE_VAPhase A Voltage RegisterSection 8.5.10
47ChPHASE_VOLTAGE_VBPhase B Voltage RegisterSection 8.5.11
47EhPHASE_VOLTAGE_VCPhase C Voltage RegisterSection 8.5.12
4B6hSIN_COMMUTATION_ANGLESine of Commutation AngleSection 8.5.13
4B8hCOS_COMMUTATION_ANGLECosine of Commutation AngleSection 8.5.14
4D2hIALPHAIALPHA Current RegisterSection 8.5.15
4D4hIBETAIBETA Current RegisterSection 8.5.16
4D6hVALPHAVALPHA Voltage RegisterSection 8.5.17
4D8hVBETAVBETA Voltage RegisterSection 8.5.18
4E2hIDMeasured d-axis Current RegisterSection 8.5.19
4E4hIQMeasured q-axis Current RegisterSection 8.5.20
4E6hVDVD Voltage RegisterSection 8.5.21
4E8hVQVQ Voltage RegisterSection 8.5.22
524hIQ_REF_ROTOR_ALIGNAlign Current ReferenceSection 8.5.23
53ChSPEED_REF_OPEN_LOOPOpen Loop Speed RegisterSection 8.5.24
54ChIQ_REF_OPEN_LOOPOpen Loop Current ReferenceSection 8.5.25
5D2hSPEED_REF_CLOSED_LOOPSpeed Reference RegisterSection 8.5.26
604hID_REF_CLOSED_LOOPReference for Current Loop RegisterSection 8.5.27
606hIQ_REF_CLOSED_LOOPReference for Current Loop RegisterSection 8.5.28
680hISD_STATEISD State RegisterSection 8.5.29
68AhISD_SPEEDISD Speed RegisterSection 8.5.30
6BEhIPD_STATEIPD State RegisterSection 8.5.31
702hIPD_ANGLECalculated IPD Angle RegisterSection 8.5.32
748hEDEstimated BEMF EQ RegisterSection 8.5.33
74AhEQEstimated BEMF ED RegisterSection 8.5.34
758hSPEED_FDBKSpeed Feedback RegisterSection 8.5.35
75ChTHETA_ESTEstimated rotor Position RegisterSection 8.5.36

Complex bit access types are encoded to fit into small table cells. Table 8-22 shows the codes that are used for access types in this section.

Table 8-22 Algorithm_Variables Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

8.5.1 ALGORITHM_STATE Register (Offset = 190h) [Reset = 0000h]

ALGORITHM_STATE is shown in Figure 8-13 and described in Table 8-23.

Return to the Summary Table.

Current Algorithm State Register

Figure 8-13 ALGORITHM_STATE Register
15141312111098
ALGORITHM_STATE
R-0h
76543210
ALGORITHM_STATE
R-0h
Table 8-23 ALGORITHM_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0ALGORITHM_STATER0h 16-bit value indicating current state of device
0h = MOTOR_IDLE
1h = MOTOR_ISD
2h = MOTOR_TRISTATE
3h = MOTOR_BRAKE_ON_START
4h = MOTOR_IPD
5h = MOTOR_SLOW_FIRST_CYCLE
6h = MOTOR_ALIGN
7h = MOTOR_OPEN_LOOP
8h = MOTOR_CLOSED_LOOP_UNALIGNED
9h = MOTOR_CLOSED_LOOP_ALIGNED
Ah = MOTOR_CLOSED_LOOP_ACTIVE_BRAKING
Bh = MOTOR_SOFT_STOP
Ch = MOTOR_RECIRCULATE_STOP
Dh = MOTOR_BRAKE_ON_STOP
Eh = MOTOR_FAULT
Fh = MOTOR_MPET_MOTOR_STOP_CHECK
10h = MOTOR_MPET_MOTOR_STOP_WAIT
11h = MOTOR_MPET_MOTOR_BRAKE
12h = MOTOR_MPET_ALGORITHM_PARAMETERS_INIT
13h = MOTOR_MPET_RL_MEASURE
14h = MOTOR_MPET_KE_MEASURE
15h = MOTOR_MPET_STALL_CURRENT_MEASURE
16h = MOTOR_MPET_TORQUE_MODE
17h = MOTOR_MPET_DONE
18h = MOTOR_MPET_FAULT

8.5.2 FG_SPEED_FDBK Register (Offset = 196h) [Reset = 00000000h]

FG_SPEED_FDBK is shown in Figure 8-14 and described in Table 8-24.

Return to the Summary Table.

Speed Feedback from FG

Figure 8-14 FG_SPEED_FDBK Register
313029282726252423222120191817161514131211109876543210
FG_SPEED_FDBK
R-0h
Table 8-24 FG_SPEED_FDBK Register Field Descriptions
BitFieldTypeResetDescription
31-0FG_SPEED_FDBKR0h 32-bit value indicating estimated rotor speed estimatedSpeed = (FG_SPEED_FDBK / 227)*MAX_SPEED in Hz

8.5.3 BUS_CURRENT Register (Offset = 410h) [Reset = 00000000h]

BUS_CURRENT is shown in Figure 8-15 and described in Table 8-25.

Return to the Summary Table.

Calculated Supply Current Register

Figure 8-15 BUS_CURRENT Register
313029282726252423222120191817161514131211109876543210
BUS_CURRENT
R-0h
Table 8-25 BUS_CURRENT Register Field Descriptions
BitFieldTypeResetDescription
31-0BUS_CURRENTR0h 32-bit value indicating DC bus current iBus = (BUS_CURRENT / 227) * Base_Current/8

8.5.4 PHASE_CURRENT_A Register (Offset = 440h) [Reset = 00000000h]

PHASE_CURRENT_A is shown in Figure 8-16 and described in Table 8-26.

Return to the Summary Table.

Measured current on Phase A Register

Figure 8-16 PHASE_CURRENT_A Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_A
R-0h
Table 8-26 PHASE_CURRENT_A Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_AR0h 32-bit value indicating measured current on Phase A iA = (PHASE_CURRENT_A / 227) * Base_Current/8

8.5.5 PHASE_CURRENT_B Register (Offset = 442h) [Reset = 00000000h]

PHASE_CURRENT_B is shown in Figure 8-17 and described in Table 8-27.

Return to the Summary Table.

Measured current on Phase B Register

Figure 8-17 PHASE_CURRENT_B Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_B
R-0h
Table 8-27 PHASE_CURRENT_B Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_BR0h 32-bit value indicating measured current on Phase B iB = (PHASE_CURRENT_B / 227) * Base_Current/8

8.5.6 PHASE_CURRENT_C Register (Offset = 444h) [Reset = 00000000h]

PHASE_CURRENT_C is shown in Figure 8-18 and described in Table 8-28.

Return to the Summary Table.

Measured current on Phase C Register

Figure 8-18 PHASE_CURRENT_C Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_C
R-0h
Table 8-28 PHASE_CURRENT_C Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_CR0h 32-bit value indicating measured current on Phase C iC = (PHASE_CURRENT_C / 227) * Base_Current/8

8.5.7 CSA_GAIN_FEEDBACK Register (Offset = 468h) [Reset = 0000h]

CSA_GAIN_FEEDBACK is shown in Figure 8-19 and described in Table 8-29.

Return to the Summary Table.

VM Voltage Register

Figure 8-19 CSA_GAIN_FEEDBACK Register
15141312111098
CSA_GAIN_FEEDBACK
R-0h
76543210
CSA_GAIN_FEEDBACK
R-0h
Table 8-29 CSA_GAIN_FEEDBACK Register Field Descriptions
BitFieldTypeResetDescription
15-0CSA_GAIN_FEEDBACKR0h 16-bit value indicating current sense gain
0h = MAX_CSA_GAIN * 8
1h = MAX_CSA_GAIN * 4
2h = MAX_CSA_GAIN * 2
3h = MAX_CSA_GAIN * 1

8.5.8 VOLTAGE_GAIN_FEEDBACK Register (Offset = 472h) [Reset = 0000h]

VOLTAGE_GAIN_FEEDBACK is shown in Figure 8-20 and described in Table 8-30.

Return to the Summary Table.

Voltage Gain Register

Figure 8-20 VOLTAGE_GAIN_FEEDBACK Register
15141312111098
VOLTAGE_GAIN_FEEDBACK
R-0h
76543210
VOLTAGE_GAIN_FEEDBACK
R-0h
Table 8-30 VOLTAGE_GAIN_FEEDBACK Register Field Descriptions
BitFieldTypeResetDescription
15-0VOLTAGE_GAIN_FEEDBACKR0h 16-bit value indicating voltage gain
0h = 60V
1h = 30V
2h = 15V

8.5.9 VM_VOLTAGE Register (Offset = 474h) [Reset = 00000000h]

VM_VOLTAGE is shown in Figure 8-21 and described in Table 8-31.

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Supply voltage register

Figure 8-21 VM_VOLTAGE Register
313029282726252423222120191817161514131211109876543210
VM_VOLTAGE
R-0h
Table 8-31 VM_VOLTAGE Register Field Descriptions
BitFieldTypeResetDescription
31-0VM_VOLTAGER0h 32-bit value indicating DC bus voltage DC Bus Voltage = VM_VOLTAGE * 60 / 227

8.5.10 PHASE_VOLTAGE_VA Register (Offset = 47Ah) [Reset = 00000000h]

PHASE_VOLTAGE_VA is shown in Figure 8-22 and described in Table 8-32.

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Phase A Voltage Register

Figure 8-22 PHASE_VOLTAGE_VA Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VA
R-0h
Table 8-32 PHASE_VOLTAGE_VA Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VAR0h 32-bit value indicating phase voltage Va during ISD Phase A voltage = PHASE_VOLTAGE_VA * 60 / (sqrt(3) * 227)

8.5.11 PHASE_VOLTAGE_VB Register (Offset = 47Ch) [Reset = 00000000h]

PHASE_VOLTAGE_VB is shown in Figure 8-23 and described in Table 8-33.

Return to the Summary Table.

Phase B Voltage Register

Figure 8-23 PHASE_VOLTAGE_VB Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VB
R-0h
Table 8-33 PHASE_VOLTAGE_VB Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VBR0h 32-bit value indicating phase voltage Vb during ISD Phase B voltage = PHASE_VOLTAGE_VB * 60 / (sqrt(3) * 227)

8.5.12 PHASE_VOLTAGE_VC Register (Offset = 47Eh) [Reset = 00000000h]

PHASE_VOLTAGE_VC is shown in Figure 8-24 and described in Table 8-34.

Return to the Summary Table.

Phase C Voltage Register

Figure 8-24 PHASE_VOLTAGE_VC Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VC
R-0h
Table 8-34 PHASE_VOLTAGE_VC Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VCR0h 32-bit value indicating phase voltage Vc during ISD Phase C voltage = PHASE_VOLTAGE_VC * 60 / (sqrt(3) * 227)

8.5.13 SIN_COMMUTATION_ANGLE Register (Offset = 4B6h) [Reset = 00000000h]

SIN_COMMUTATION_ANGLE is shown in Figure 8-25 and described in Table 8-35.

Return to the Summary Table.

Sine of Commutation Angle

Figure 8-25 SIN_COMMUTATION_ANGLE Register
313029282726252423222120191817161514131211109876543210
SIN_COMMUTATION_ANGLE
R-0h
Table 8-35 SIN_COMMUTATION_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0SIN_COMMUTATION_ANGLER0h 32-bit value indicating sine of commutation Angle sinCommutationAngle = (SIN_COMMUTATION_ANGLE / 227)

8.5.14 COS_COMMUTATION_ANGLE Register (Offset = 4B8h) [Reset = 00000000h]

COS_COMMUTATION_ANGLE is shown in Figure 8-26 and described in Table 8-36.

Return to the Summary Table.

Cosine of Commutation Angle

Figure 8-26 COS_COMMUTATION_ANGLE Register
313029282726252423222120191817161514131211109876543210
COS_COMMUTATION_ANGLE
R-0h
Table 8-36 COS_COMMUTATION_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0COS_COMMUTATION_ANGLER0h 32-bit value indicating cosine of commutation Angle cosCommutationAngle = (COS_COMMUTATION_ANGLE / 227)

8.5.15 IALPHA Register (Offset = 4D2h) [Reset = 00000000h]

IALPHA is shown in Figure 8-27 and described in Table 8-37.

Return to the Summary Table.

IALPHA Current Register

Figure 8-27 IALPHA Register
313029282726252423222120191817161514131211109876543210
IALPHA
R-0h
Table 8-37 IALPHA Register Field Descriptions
BitFieldTypeResetDescription
31-0IALPHAR0h 32-bit value indicating calculated IALPHA iAlpha = (IALPHA / 227) * Base_Current/8

8.5.16 IBETA Register (Offset = 4D4h) [Reset = 00000000h]

IBETA is shown in Figure 8-28 and described in Table 8-38.

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IBETA Current Register

Figure 8-28 IBETA Register
313029282726252423222120191817161514131211109876543210
IBETA
R-0h
Table 8-38 IBETA Register Field Descriptions
BitFieldTypeResetDescription
31-0IBETAR0h 32-bit value indicating calculated IBETA iBeta = (IBETA / 227) * Base_Current/8

8.5.17 VALPHA Register (Offset = 4D6h) [Reset = 00000000h]

VALPHA is shown in Figure 8-29 and described in Table 8-39.

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VALPHA Voltage Register

Figure 8-29 VALPHA Register
313029282726252423222120191817161514131211109876543210
VALPHA
R-0h
Table 8-39 VALPHA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALPHAR0h 32-bit value indicating calculated VALPHA vAlpha = (VALPHA / 227) * 60 / sqrt(3)

8.5.18 VBETA Register (Offset = 4D8h) [Reset = 00000000h]

VBETA is shown in Figure 8-30 and described in Table 8-40.

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VBETA Voltage Register

Figure 8-30 VBETA Register
313029282726252423222120191817161514131211109876543210
VBETA
R-0h
Table 8-40 VBETA Register Field Descriptions
BitFieldTypeResetDescription
31-0VBETAR0h 32-bit value indicating calculated VBETA vBeta = (VBETA / 227) * 60 / sqrt(3)

8.5.19 ID Register (Offset = 4E2h) [Reset = 00000000h]

ID is shown in Figure 8-31 and described in Table 8-41.

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Measured d-axis Current Register

Figure 8-31 ID Register
313029282726252423222120191817161514131211109876543210
ID
R-0h
Table 8-41 ID Register Field Descriptions
BitFieldTypeResetDescription
31-0IDR0h 32-bit value indicating estimated Id id = (ID / 227) * Base_Current/8

8.5.20 IQ Register (Offset = 4E4h) [Reset = 00000000h]

IQ is shown in Figure 8-32 and described in Table 8-42.

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Measured q-axis Current Register

Figure 8-32 IQ Register
313029282726252423222120191817161514131211109876543210
IQ
R-0h
Table 8-42 IQ Register Field Descriptions
BitFieldTypeResetDescription
31-0IQR0h 32-bit value indicating estimated Iq iq = (IQ / 227) * Base_Current/8

8.5.21 VD Register (Offset = 4E6h) [Reset = 00000000h]

VD is shown in Figure 8-33 and described in Table 8-43.

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VD Voltage Register

Figure 8-33 VD Register
313029282726252423222120191817161514131211109876543210
VD
R-0h
Table 8-43 VD Register Field Descriptions
BitFieldTypeResetDescription
31-0VDR0h 32-bit value indicating applied Vd vd = (VD / 227) * 60 / sqrt(3)

8.5.22 VQ Register (Offset = 4E8h) [Reset = 00000000h]

VQ is shown in Figure 8-34 and described in Table 8-44.

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VQ Voltage Register

Figure 8-34 VQ Register
313029282726252423222120191817161514131211109876543210
VQ
R-0h
Table 8-44 VQ Register Field Descriptions
BitFieldTypeResetDescription
31-0VQR0h 32-bit value indicating applied Vq vq = (VQ / 227) * 60 / sqrt(3)

8.5.23 IQ_REF_ROTOR_ALIGN Register (Offset = 524h) [Reset = 00000000h]

IQ_REF_ROTOR_ALIGN is shown in Figure 8-35 and described in Table 8-45.

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Align Current Reference

Figure 8-35 IQ_REF_ROTOR_ALIGN Register
313029282726252423222120191817161514131211109876543210
IQ_REF_ROTOR_ALIGN
R-0h
Table 8-45 IQ_REF_ROTOR_ALIGN Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_ROTOR_ALIGNR0h 32-bit value indicating align current reference iqRefRotorAlign = (IQ_REF_ROTOR_ALIGN / 227) * Base_Current/8

8.5.24 SPEED_REF_OPEN_LOOP Register (Offset = 53Ch) [Reset = 00000000h]

SPEED_REF_OPEN_LOOP is shown in Figure 8-36 and described in Table 8-46.

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Speed at which motor transitions to close loop

Figure 8-36 SPEED_REF_OPEN_LOOP Register
313029282726252423222120191817161514131211109876543210
SPEED_REF_OPEN_LOOP
R-0h
Table 8-46 SPEED_REF_OPEN_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_REF_OPEN_LOOPR0h 32-bit value indicating open loop speed openLoopSpeedRef = (SPEED_REF_OPEN_LOOP / 227) * MAX_SPEED in Hz

8.5.25 IQ_REF_OPEN_LOOP Register (Offset = 54Ch) [Reset = 00000000h]

IQ_REF_OPEN_LOOP is shown in Figure 8-37 and described in Table 8-47.

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Open Loop Current Reference

Figure 8-37 IQ_REF_OPEN_LOOP Register
313029282726252423222120191817161514131211109876543210
IQ_REF_OPEN_LOOP
R-0h
Table 8-47 IQ_REF_OPEN_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_OPEN_LOOPR0h 32-bit value indicating open loop current reference iqRefOpenLoop = (IQ_REF_OPEN_LOOP / 227) * Base_Current/8

8.5.26 SPEED_REF_CLOSED_LOOP Register (Offset = 5D2h) [Reset = 00000000h]

SPEED_REF_CLOSED_LOOP is shown in Figure 8-38 and described in Table 8-48.

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Speed Reference Register

Figure 8-38 SPEED_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
SPEED_REF_CLOSED_LOOP
R-0h
Table 8-48 SPEED_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_REF_CLOSED_LOOPR0h 32-bit value indicating reference for speed loop Speed reference in closed loop (Hz) = (SPEED_REF_CLOSED_LOOP/ 227) * MAX_SPEED in Hz

8.5.27 ID_REF_CLOSED_LOOP Register (Offset = 604h) [Reset = 00000000h]

ID_REF_CLOSED_LOOP is shown in Figure 8-39 and described in Table 8-49.

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Reference for Current Loop Register

Figure 8-39 ID_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
ID_REF_CLOSED_LOOP
R-0h
Table 8-49 ID_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_REF_CLOSED_LOOPR0h 32-bit value indicating Id_ref for flux loop idRefClosedLoop = (ID_REF_CLOSED_LOOP / 227) * Base_Current/8

8.5.28 IQ_REF_CLOSED_LOOP Register (Offset = 606h) [Reset = 00000000h]

IQ_REF_CLOSED_LOOP is shown in Figure 8-40 and described in Table 8-50.

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Reference for Current Loop Register

Figure 8-40 IQ_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
IQ_REF_CLOSED_LOOP
R-0h
Table 8-50 IQ_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_CLOSED_LOOPR0h 32-bit value indicating Iq_ref for torque loop iqRefClosedLoop = (IQ_REF_CLOSED_LOOP / 227) * Base_Current/8

8.5.29 ISD_STATE Register (Offset = 680h) [Reset = 0000h]

ISD_STATE is shown in Figure 8-41 and described in Table 8-51.

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ISD state Register

Figure 8-41 ISD_STATE Register
15141312111098
ISD_STATE
R-0h
76543210
ISD_STATE
R-0h
Table 8-51 ISD_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0ISD_STATER0h 16-bit value indicating current ISD state
0h = ISD_INIT
1h = ISD_MOTOR_STOP_CHECK
2h = ISD_ESTIM_INIT
3h = ISD_RUN_MOTOR_CHECK
4h = ISD_MOTOR_DIRECTION_CHECK
5h = ISD_COMPLETE
6h = ISD_FAULT

8.5.30 ISD_SPEED Register (Offset = 68Ah) [Reset = 00000000h]

ISD_SPEED is shown in Figure 8-42 and described in Table 8-52.

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ISD Speed Register

Figure 8-42 ISD_SPEED Register
313029282726252423222120191817161514131211109876543210
ISD_SPEED
R-0h
Table 8-52 ISD_SPEED Register Field Descriptions
BitFieldTypeResetDescription
31-0ISD_SPEEDR0h 32-bit value indicating calculated speed during ISD state isdSpeed = (ISD_SPEED / 227) * MAX_SPEED in Hz

8.5.31 IPD_STATE Register (Offset = 6BEh) [Reset = 0000h]

IPD_STATE is shown in Figure 8-43 and described in Table 8-53.

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IPD state Register

Figure 8-43 IPD_STATE Register
15141312111098
IPD_STATE
R-0h
76543210
IPD_STATE
R-0h
Table 8-53 IPD_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0IPD_STATER0h 16-bit value indicating current IPD state
0h = IPD_INIT
1h = IPD_VECTOR_CONFIG
2h = IPD_RUN
3h = IPD_SLOW_RISE_CLOCK
4h = IPD_SLOW_FALL_CLOCK
5h = IPD_WAIT_CURRENT_DECAY
6h = IPD_GET_TIMES
7h = IPD_SET_NEXT_VECTOR
8h = IPD_CALC_SECTOR_RISE
9h = IPD_CALC_ROTOR_POSITION
Ah = IPD_CALC_ANGLE
Bh = IPD_COMPLETE
Ch = IPD_FAULT

8.5.32 IPD_ANGLE Register (Offset = 702h) [Reset = 00000000h]

IPD_ANGLE is shown in Figure 8-44 and described in Table 8-54.

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Calculated IPD Angle Register

Figure 8-44 IPD_ANGLE Register
313029282726252423222120191817161514131211109876543210
IPD_ANGLE
R-0h
Table 8-54 IPD_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0IPD_ANGLER0h 32-bit value indicating measured IPD angle ipdAngle = (IPD_ANGLE / 227) * 360 (Degree)

8.5.33 ED Register (Offset = 748h) [Reset = 00000000h]

ED is shown in Figure 8-45 and described in Table 8-55.

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Estimated BEMF EQ Register

Figure 8-45 ED Register
313029282726252423222120191817161514131211109876543210
ED
R-0h
Table 8-55 ED Register Field Descriptions
BitFieldTypeResetDescription
31-0EDR0h 32-bit value indicating estimated ED Ed = (ED / 227) * 60 / sqrt(3)

8.5.34 EQ Register (Offset = 74Ah) [Reset = 00000000h]

EQ is shown in Figure 8-46 and described in Table 8-56.

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Estimated BEMF ED Register

Figure 8-46 EQ Register
313029282726252423222120191817161514131211109876543210
EQ
R-0h
Table 8-56 EQ Register Field Descriptions
BitFieldTypeResetDescription
31-0EQR0h 32-bit value indicating estimated EQ Eq = (EQ / 227) * 60 / sqrt(3)

8.5.35 SPEED_FDBK Register (Offset = 758h) [Reset = 00000000h]

SPEED_FDBK is shown in Figure 8-47 and described in Table 8-57.

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Speed Feedback Register

Figure 8-47 SPEED_FDBK Register
313029282726252423222120191817161514131211109876543210
SPEED_FDBK
R-0h
Table 8-57 SPEED_FDBK Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_FDBKR0h 32-bit value indicating estimated rotor speed estimatedSpeed = (SPEED_FDBK / 227)*MAX_SPEED in Hz

8.5.36 THETA_EST Register (Offset = 75Ch) [Reset = 00000000h]

THETA_EST is shown in Figure 8-48 and described in Table 8-58.

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Estimated rotor Position Register

Figure 8-48 THETA_EST Register
313029282726252423222120191817161514131211109876543210
THETA_EST
R-0h
Table 8-58 THETA_EST Register Field Descriptions
BitFieldTypeResetDescription
31-0THETA_ESTR0h 32-bit value indicating estimated rotor angle estimatedAngle = (THETA_EST / 227)*360 (Degree)