SLLSFZ8A November   2025  – March 2026 MCF8329HS-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Three Phase BLDC Gate Drivers
      2. 6.3.2  Gate Drive Architecture
        1. 6.3.2.1 Dead time and Cross Conduction Prevention
      3. 6.3.3  AVDD Linear Voltage Regulator
      4. 6.3.4  Low-Side Current Sense Amplifier
      5. 6.3.5  Device Interface Modes
        1. 6.3.5.1 Interface - Control and Monitoring
        2. 6.3.5.2 I2C Interface
      6. 6.3.6  Motor Control Input Options
        1. 6.3.6.1 Analog-Mode Motor Control
        2. 6.3.6.2 PWM-Mode Motor Control
        3. 6.3.6.3 Frequency-Mode Motor Control
        4. 6.3.6.4 I2C based Motor Control
        5. 6.3.6.5 Input Control Signal Profiles
          1. 6.3.6.5.1 Linear Control Profiles
          2. 6.3.6.5.2 Staircase Control Profiles
          3. 6.3.6.5.3 Forward-Reverse Profiles
          4. 6.3.6.5.4 Multi-Reference Mode Operation
          5. 6.3.6.5.5 Input Reference Transfer Function without Profiler
      7. 6.3.7  Bootstrap Capacitor Initial Charging
      8. 6.3.8  Starting the Motor Under Different Initial Conditions
        1. 6.3.8.1 Case 1 – Motor is Stationary
        2. 6.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 6.3.9  Motor Start Sequence (MSS)
        1. 6.3.9.1 Initial Speed Detect (ISD)
        2. 6.3.9.2 Motor Resynchronization
        3. 6.3.9.3 Reverse Drive
          1. 6.3.9.3.1 Reverse Drive Tuning
        4. 6.3.9.4 Motor Start-up
          1. 6.3.9.4.1 Align
          2. 6.3.9.4.2 Double Align
          3. 6.3.9.4.3 Initial Position Detection (IPD)
            1. 6.3.9.4.3.1 IPD Operation
            2. 6.3.9.4.3.2 IPD Release
            3. 6.3.9.4.3.3 IPD Advance Angle
          4. 6.3.9.4.4 Slow First Cycle Startup
          5. 6.3.9.4.5 Open Loop
          6. 6.3.9.4.6 Transition from Open to Closed Loop
      10. 6.3.10 Closed Loop Operation
        1. 6.3.10.1 Closed loop accelerate
        2. 6.3.10.2 Speed PI Control
        3. 6.3.10.3 Current PI Control
        4. 6.3.10.4 Overmodulation
        5. 6.3.10.5 Power Loop
        6. 6.3.10.6 Modulation Index Control
        7. 6.3.10.7 Motor Speed Limit
        8. 6.3.10.8 Input DC Power Limit
      11. 6.3.11 Maximum Torque Per Ampere (MTPA) Control
      12. 6.3.12 Flux Weakening Control
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Single Hall Sensor Operation
      16. 6.3.16 Anti-Voltage Surge (AVS)
      17. 6.3.17 Active Braking
      18. 6.3.18 Output PWM Switching Frequency
      19. 6.3.19 PWM Dithering
      20. 6.3.20 Voltage Sense Scaling
      21. 6.3.21 Motor Stop Options
        1. 6.3.21.1 Coast (Hi-Z) Mode
        2. 6.3.21.2 Low-Side Braking
        3. 6.3.21.3 Active Spin-Down
      22. 6.3.22 FG Configuration
        1. 6.3.22.1 FG Output Frequency
        2. 6.3.22.2 FG in Open-Loop
        3. 6.3.22.3 FG During Motor Stop
        4. 6.3.22.4 FG Behavior During Fault
      23. 6.3.23 Protections
        1. 6.3.23.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 6.3.23.2  AVDD Power on Reset (AVDD_POR)
        3. 6.3.23.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 6.3.23.4  BST Undervoltage Lockout (BST_UV)
        5. 6.3.23.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 6.3.23.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 6.3.23.7  Thermal Shutdown (OTSD)
        8. 6.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 6.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 6.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 110b)
          4. 6.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE = 111b)
        9. 6.3.23.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 6.3.23.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 6.3.23.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 6.3.23.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 110b)
          4. 6.3.23.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 111b)
        10. 6.3.23.10 Motor Lock (MTR_LCK)
          1. 6.3.23.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xb or 010b)
          2. 6.3.23.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE = 011b or 10xb)
          3. 6.3.23.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 110b)
          4. 6.3.23.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 111b)
        11. 6.3.23.11 Motor Lock Detection
          1. 6.3.23.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.23.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.23.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 6.3.23.12 EEPROM Fault
        13. 6.3.23.13 I2C CRC Fault
        14. 6.3.23.14 Maximum PVDD (Overvoltage) Protection
        15. 6.3.23.15 Minimum PVDD (Undervoltage) Protection
        16. 6.3.23.16 MPET Faults
        17. 6.3.23.17 Dry Run Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 6.5.2 Oscillator Source
        1. 6.5.2.1 Clock (Internal Oscillator) Frequency
      3. 6.5.3 External Watchdog with MCU Reset
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
        3. 6.6.1.3 EEPROM Security
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 Examples of I2C Communication Protocol Packets
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
  8. 7 EEPROM (Non-Volatile) Register Map
    1. 7.1 Algorithm_Configuration Registers
    2. 7.2 Fault_Configuration Registers
    3. 7.3 Hardware_Configuration Registers
    4. 7.4 Internal_Algorithm_Configuration Registers
  9. 8 RAM (Volatile) Register Map
    1. 8.1 Fault_Status Registers
    2. 8.2 System_Status Registers
    3. 8.3 Algorithm_Control Registers
    4. 8.4 Device_Control Registers
    5. 8.5 Algorithm_Variables Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3.      Gate Drive Current
      4.      Gate Resistor Selection
      5.      System Considerations in High Power Designs
      6.      Capacitor Voltage Ratings
      7.      External Power Stage Components
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
        1. 9.4.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5.2.1 Clock (Internal Oscillator) Frequency

MCF8329HS-Q1 provides configurable clock (internal oscillator) frequency to optimize between device operating current and maximum motor speed/PWM switching frequency. Table 6-10 shows the relationship between clock frequency, PWM switching frequency and maximum motor speed.

Table 6-10 Maximum motor speed vs PWM switching frequency vs clock frequency
PWM_FREQ_OUT PWM Switching Frequency (kHz) Maximum Motor Speed (Hz)
CLOCK_FREQUENCY = HIGH CLOCK_FREQUENCY = MEDIUM CLOCK_FREQUENCY = LOW
0000b 10 1200 1200 1000
0001b 15 1800 1800 900
0010b 20 2500 1200 1000
0011b 25 1500 1500 1000
0100b 30 1800 1800 1000
0101b 35 2150 1450 1000
0110b 40 2500 1600 1000
0111b 45 1800 1800 1000
1000b 50 2000 1500 1000
1001b 55 2300 1700 Not Applicable
1010b 60 2500 1500 Not Applicable
1011b 65 2000 1600 Not Applicable
1100b 70 2100 1750 Not Applicable
1101b 75 2300 1500 Not Applicable
1110b 80 2000 1600 Not Applicable
Note: Any change to CLOCK_FREQUENCY setting can take effect only after writing to EEPROM followed by a power recycle.

Clock frequency impacts the applied dead time configured by DIG_DEAD_TIME. Table 6-11 shows the applied dead time as a function of clock frequency.

Table 6-11 Dead time vs clock frequency
DIG_DEAD_TIME Dead time (ns)
CLOCK_FREQUENCY = HIGH CLOCK_FREQUENCY = MEDIUM CLOCK_FREQUENCY = LOW
0000b 0 0 0
0001b 75 50 75
0010b 150 100 110
0011b 150 150 150
0100b 225 200 225
0101b 300 250 260
0110b 300 300 300
0111b 375 350 375
1000b 450 400 450
1001b 450 450 450
1010b 525 500 520
1011b 600 600 600
1100b 750 700 750
1101b 900 800 750
1110b 1050 1000 750