SLLSG26A March   2026  – July 2026 ISOW1050

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Supply Current Characteristics
    11. 5.11 Switching Characteristics
    12. 5.12 Insulation Characteristics Curves
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Power Isolation
    3. 7.3 Signal Isolation
    4. 7.4 CAN Transceiver
    5. 7.5 Functional Block Diagram
    6. 7.6 Feature Description
      1. 7.6.1 CAN Bus States
      2. 7.6.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
      3. 7.6.3 TXD Dominant Timeout (DTO)
      4. 7.6.4 Power-Up and Power-Down Behavior
      5. 7.6.5 Protection Features
      6. 7.6.6 Floating Pins, Unpowered Device
      7. 7.6.7 Glitch-Free Power Up and Power Down
    7. 7.7 Device Functional Modes
    8. 7.8 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Bus Loading, Length and Number of Nodes
        2. 8.2.2.2 CAN Termination
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6.3 TXD Dominant Timeout (DTO)

The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge occurs before the timeout period expires, which frees the bus for communication between other nodes on the network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased to the recessive level during a TXD dominant timeout.

ISOW1050 Example Timing Diagram for TXD DTOFigure 7-5 Example Timing Diagram for TXD DTO
Note:

The minimum dominant TXD time (tTXD_DTO) allowed by the TXD DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum transmitted data rate with Equation 1.

Equation 1. Minimum Data Rate=11tTXD_DTO