SLLU091A January   2006  – September 2022 ISO721 , ISO721M

 

  1. 1Introduction
  2. 2Overview
  3. 3Functional Configuration of the ISO721 and ISO721M
  4. 4EVM Signal Paths of the ISO721 and ISO721M Isolators
  5. 5The EVM Configuration
  6. 6EVM Setup and Operation
    1. 6.1 Overview
  7. 7Revision History

Overview

The ISO721 and ISO721M digital isolators have a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. Used with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.

A binary input signal is conditioned, translated to a balanced signal, and then differentiated by the SiO2 isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 μs, the input is assumed to be unpowered or not functional, and the fail-safe circuit drives the output to a logic-high state.

CAUTION:

Note that although these devices provide galvanic isolation of up to 4000 V, this EVM cannot be used for isolation voltage testing. It is designed for the examination of device operating parameters only and will be damaged if high voltage (> 5.5 V) is applied anywhere in the circuit.