SLLU255A October   2016  – November 2024 TUSB1046-DCI , TUSB1046A-DCI

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 TUSB1046EVM-SRC Test Board Setup
    3. 2.3 TUSB1046 EVM Default EQ Configuration
      1. 2.3.1 TUSB1046 EQ Control
  9. 3Software
    1. 3.1 Firmware Description
  10. 4Hardware Design Files
    1. 4.1 TUSB1046EVM Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Related Documentation
  13. 7Revision History

2.3 TUSB1046 EVM Default EQ Configuration

The headers in Table 2-1 are provided for TUSB1046 EQ configuration by default, configuration settings may need to be optimized depending on the amount of loss of each channel in the system.

Table 2-1 TUSB1046 Configuration Pins
Reference Designator JMP Control Configuration

JMP2

I2C_EN

SHUNT on pin 2-3 (0 - 1k to GND)
JMP3 Downstream EQ0 SHUNT on pin 1-2 (1 - 1k to VCC)
JMP4 Downstream EQ1 SHUNT on pin 2-4 (R – 20k to GND)
JMP5 Upstream SSEQ0 SHUNT on pin 1-2 (1 – 1k to VCC)
JMP6 Upstream SSEQ1 SHUNT on pin 2-4 (R – 20k to GND)
JMP7 DP EQ0 SHUNT on pin 2-3 (0 – 1k to GND)
JMP8 DP EQ1 SHUNT on pin 2-4 (R – 20k to GND)