SLOA140B April   2009  – November 2018 TRF7960 , TRF7960A , TRF7961 , TRF7962A , TRF7963A

 

  1.   Using the SPI Interface With TRF7960
    1.     Trademarks
    2. 1 TRF7960 - SPI With SS* Mode Errata
      1. 1.1 SCLK Polarity Switch
      2. 1.2 IRQ Status Register Read
      3. 1.3 Direct Command Processing
      4. 1.4 Initialization of Derivative Registers
      5. 1.5 Transmitting One Byte Through the FIFO
      6. 1.6 Extra Dummy Bytes on RX
      7. 1.7 Timing Conditions for MOSI With Respect to S_CLK
  2.   Revision History

1.2 IRQ Status Register Read

NOTE

Special steps are needed when you read the TRF796x IRQ status register (register address 0x0C) in SPI mode. The status of the bits in this register are cleared after a “dummy read”. The following steps need to be followed when reading the IRQ status register.
  1. Write in command 0x6C: read 'IRQ status' register in continuous mode (8 clocks).
  2. Read out the data in register 0x0C (8 clocks).
  3. Generate another 8 clocks (as you were reading the data in register 0x0D) but ignore the MISO data line.

This is shown in Figure 4.

irq_read_loa140.gifFigure 4. SPI Interface Communication (IRQ Status Register Read)