SLUAA33A April   2020  – October 2022 BQ25970

 

  1.   How to use the BQ25970 for Flash Charging
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Key BQ25970 Specifications
    2. 1.2 BQ25970 Simplified Power Stage
  4. 2PPS Protocols for BQ25970
    1. 2.1 What is the PPS Protocol?
    2. 2.2 PPS Protocol Working Process Sample
  5. 3Key Design Tips for BQ25970
    1. 3.1 Simplified Schematic
    2. 3.2 How to Translate R on Power Trace From input to Output of BQ25970 or Reversely
    3. 3.3 PCB Layout Tips for BQ25970
  6. 4References
  7. 5Revision History

3.3 PCB Layout Tips for BQ25970

Proper PCB layout ensures good performance, so the designer must pay attention on PCB layout as the PCB layout sample in Figure 3-5 shows.

GUID-CF7D15F3-47AA-4034-A863-41B00A10AEA4-low.pngFigure 3-5 BQ25970 PCB Layout
  • CFLY capacitors are placed close to the BQ25970 device, the power trace should be short and wide to decrease power loss on the PCB trace.
  • Connect the GND pin to the main ground plane directly to get better thermal sink and better EMI performance.
  • The width of the external MOSFET gate driving trace between the OVPGATE pin and the external MOSFET gate should be 10 mil or more because of high di/dt when OVPGATE is active. Also, it is better to surround this driving trace with a ground wire to avoid any noise interference.
  • The battery sense trace BATP and BATN should be routed as differential traces, and connect them to the battery socket terminal directly. If possible, surround them with ground trace to avoid noise interference.