SLUAA53 October   2020 TPS628501-Q1 , TPS628502-Q1

 

  1. 1Overview
  2. 2Functional Safety Failure In Time (FIT) Rates
  3. 3Failure Mode Distribution (FMD)
  4. 4Pin Failure Mode Analysis (Pin FMA)

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for TPS62850x-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)

SW no output

35%

SW output not in specification - voltage or timing

45%

SW power HS or LS FET stuck on

10%

PG false trip or fails to trip

5%

Short circuit any two pins

5%