2 EN to VCC Start-up Time

Figure 2-1 below shows the typical timing diagram of VCC rising of the device, once the enable signal crosses 0.932V typical threshold, VCC start rising after t_VCCDLY time. Typical value of t_VCCDLY = 13.5us and can vary from 6.35us to 25.6us.

Figure 2-1 EN to VCC Start-up Delay