SLUAB45 October   2026 UCD3138

 

  1.   1
  2.   Abstract
  3. 1Issue Description: Abnormal SR Voltage Stress Under Output Short-Circuit
    1. 1.1 Abnormal Phenomenon: SR Voltage Stress Exceeds the Limit in Short-Circuit Testing
    2. 1.2 Root Cause Analysis: Timing Mechanism of Turn-Off Stress Caused by Negative Current
  4. 2Solution: SR Stress Optimization Based on the UCD3138 Automatic Mode Switching Capability
    1. 2.1 Key Technology: Principle of the UCD3138 Automatic Mode Switching Capability
    2. 2.2 Solution Implementation: Dynamically Adjusting the Control Timing of the SR On-Time With Mode Switching
  5. 3Experimental Verification: Effectiveness Testing of the Optimization Solution
    1. 3.1 Result Comparison: SR Stress Reduced From 69V to 29.6V
    2. 3.2 Waveform Analysis: Dynamic Switching of the SR On-Time and Early Turn-Off
  6. 4Conclusion
  7. 5References

Result Comparison: SR Stress Reduced From 69V to 29.6V

To verify the effectiveness of the above solution, tests were performed on the PMP40586 reference design platform. Figure 3-1 shows the waveforms for output short-circuit testing after optimization using the automatic mode switching capability. It is clearly shown that the maximum voltage stress across the SR is limited to 29.6V, which is significantly lower than the 69V (Figure 1-2) before optimization and is within the safe operating range of the device.

 SR Stress Waveform Under Output Short-Circuit Using the Optimization SolutionFigure 3-1 SR Stress Waveform Under Output Short-Circuit Using the Optimization Solution