SLUS714E January   2007  – June 2019 TPS40077

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum Pulse Duration
      2. 7.3.2  Slew Rate Limit On VDD
      3. 7.3.3  Setting The Switching Frequency (Programming The Clock Oscillator)
      4. 7.3.4  Loop Compensation
      5. 7.3.5  Shutdown and Sequencing
      6. 7.3.6  Boost and LVBP Bypass Capacitance
      7. 7.3.7  Internal Regulators
      8. 7.3.8  Power Dissipation
      9. 7.3.9  Boost Diode
      10. 7.3.10 Synchronous Rectifier Control
    4. 7.4 Programming
      1. 7.4.1 Programming The Ramp Generator Circuit and UVLO
      2. 7.4.2 Programming Soft Start
      3. 7.4.3 Programming Short-Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Regulator 8-V to 16-V Input, 1.8-V Output at 10 A
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Power Train Components
            1. 8.2.1.2.1.1  Output Inductor, LOUT
            2. 8.2.1.2.1.2  Output Capacitor, COUT, ELCO and MLCC
            3. 8.2.1.2.1.3  Input Capacitor, CIN ELCO and MLCC
            4. 8.2.1.2.1.4  Switching MOSFET, QSW
            5. 8.2.1.2.1.5  Rectifier MOSFET, QSR
            6. 8.2.1.2.1.6  Timing Resistor, RT
            7. 8.2.1.2.1.7  Feed-Forward and UVLO Resistor, RKFF
            8. 8.2.1.2.1.8  Soft-Start Capacitor, CSS
            9. 8.2.1.2.1.9  Short-Circuit Protection, RILIM and CILIM
            10. 8.2.1.2.1.10 Boost Voltage, CBOOST and DBOOST (Optional)
            11. 8.2.1.2.1.11 Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1
        3. 8.2.1.3 Application Curves
    3. 8.3 Additional System Examples
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

9.1 Layout Guidelines

The TPS40077 provides separate signal ground (SGND) and power ground (PGND) pins. Take care to properly separation of the circuit grounds. Each ground must consist of a plane to minimize its impedance, if possible. The high-power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (DBP), and the input capacitor should be connected to PGND plane.

Connect sensitive nodes such as the FB resistor divider and RT to the SGND plane. The SGND plane must only make a single-point connection to the PGND plane. TI recommends that the SGND pin be tied to the copper area for the thermal pad underneath the chip. Tie the PGND to the thermal-pad copper area as well, and make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the SGND pin.

Component placement must ensure that bypass capacitors (LVPB and DBP) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high-dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout practices results in suboptimal operation. More detailed information can be found in the TPS40077EVM user's guide (SLVU192).