SLUSAY8G June   2012  – November 2025 TPS53318 , TPS53319

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
    7. 6.7 TPS53319 Typical Characteristics
    8. 6.8 TPS53318 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  5-V LDO and VREG Start-Up
      2. 7.3.2  Adaptive On-Time D-CAP™ Integrated Circuit Control and Frequency Selection
      3. 7.3.3  Ramp Signal
      4. 7.3.4  Adaptive Zero Crossing
      5. 7.3.5  Output Discharge Control
      6. 7.3.6  Power Good
      7. 7.3.7  Current Sense, Overcurrent, and Short-Circuit Protection
      8. 7.3.8  Overvoltage and Undervoltage Protection
      9. 7.3.9  Redundant Overvoltage Protection (OVP)
      10. 7.3.10 UVLO Protection
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Small Signal Model
      13. 7.3.13 External Component Selection Using All Ceramic Output Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Soft Start, and Mode Selection
      2. 7.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Using Bulk Output Capacitors, Redundant Overvoltage Protection Function (OVP) Disabled
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Step One: Select Operation Mode and Soft-Start Time
          2. 8.2.1.2.2 Step Two: Select Switching Frequency
          3. 8.2.1.2.3 Step Three: Choose the Inductor
          4. 8.2.1.2.4 Step Four: Choose the Output Capacitor or Capacitors
          5. 8.2.1.2.5 Step Five: Determine the Value of R1 and R2
          6. 8.2.1.2.6 Step Six: Choose the Overcurrent Setting Resistor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Application Using Ceramic Output Capacitors, Redundant Overvoltage Protection Function (OVP) Enabled
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Component Selection Using All Ceramic Output Capacitors
          2. 8.2.2.2.2 Redundant Overvoltage Protection
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.13 External Component Selection Using All Ceramic Output Capacitors

When a ceramic output capacitor is used, the stability criteria in Equation 7 cannot be satisfied. The ripple injection approach as shown in Figure 8-1 is implemented to increase the ripple on the VFB pin and make the system stable. In addition to the selections made using steps 1 through step 6 in Section 8.2.1.2, the ripple injection components must be selected. The C2 value can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF.

Equation 8. TPS53318 TPS53319

where

  • N is the coefficient to account for L and COUT variation

N is also used to provide enough margin for stability. TI recommends that N = 2 for VOUT ≤ 1.8 V and N = 4 for VOUT ≥ 3.3 V or when L ≤ 250 nH. The higher VOUT needs a higher N value because the effective output capacitance is reduced significantly with higher DC bias. For example, a 6.3-V, 22-µF ceramic capacitor can have only 8 µF of effective capacitance when biased at 5 V.

Because the VFB pin voltage is regulated at the valley, the increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node and the other coupled from the VOUT pin and the components can be calculated using Equation 9 and Equation 10 when neglecting the output voltage ripple caused by equivalent series inductance (ESL).

Equation 9. TPS53318 TPS53319
Equation 10. TPS53318 TPS53319

TI recommends that VINJ_SW to be less than 50 mV. If the calculated VINJ_SW is higher than 50 mV, then other parameters need to be adjusted to reduce VINJ_SW. For example, COUT can be increased to satisfy Equation 8 with a higher R7 value, thereby reducing VINJ_SW.

The DC voltage at the VFB pin can be calculated by Equation 11:

Equation 11. TPS53318 TPS53319

And the resistor divider value can be determined by Equation 12:

Equation 12. TPS53318 TPS53319