SLUSAY8G June   2012  – November 2025 TPS53318 , TPS53319

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
    7. 6.7 TPS53319 Typical Characteristics
    8. 6.8 TPS53318 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  5-V LDO and VREG Start-Up
      2. 7.3.2  Adaptive On-Time D-CAP™ Integrated Circuit Control and Frequency Selection
      3. 7.3.3  Ramp Signal
      4. 7.3.4  Adaptive Zero Crossing
      5. 7.3.5  Output Discharge Control
      6. 7.3.6  Power Good
      7. 7.3.7  Current Sense, Overcurrent, and Short-Circuit Protection
      8. 7.3.8  Overvoltage and Undervoltage Protection
      9. 7.3.9  Redundant Overvoltage Protection (OVP)
      10. 7.3.10 UVLO Protection
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Small Signal Model
      13. 7.3.13 External Component Selection Using All Ceramic Output Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Soft Start, and Mode Selection
      2. 7.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Using Bulk Output Capacitors, Redundant Overvoltage Protection Function (OVP) Disabled
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Step One: Select Operation Mode and Soft-Start Time
          2. 8.2.1.2.2 Step Two: Select Switching Frequency
          3. 8.2.1.2.3 Step Three: Choose the Inductor
          4. 8.2.1.2.4 Step Four: Choose the Output Capacitor or Capacitors
          5. 8.2.1.2.5 Step Five: Determine the Value of R1 and R2
          6. 8.2.1.2.6 Step Six: Choose the Overcurrent Setting Resistor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Application Using Ceramic Output Capacitors, Redundant Overvoltage Protection Function (OVP) Enabled
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Component Selection Using All Ceramic Output Capacitors
          2. 8.2.2.2.2 Redundant Overvoltage Protection
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.1 5-V LDO and VREG Start-Up

Both the TPS53318 and TPS53319 devices provide an internal 5-V LDO function using input from VDD and output to VREG. When the VDD voltage rises above 2 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG voltage provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drives.

TPS53318 TPS53319 Power-Up Sequence Voltage WaveformsFigure 7-1 Power-Up Sequence Voltage Waveforms
Note:

The 5-V LDO is not controlled by the EN pin. The LDO starts-up any time VDD rises to approximately 2 V (see Figure 7-1).