SLUSDM0N May   2020  – January 2026 TPS628501-Q1 , TPS628502-Q1 , TPS628503-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Schematic
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precise Enable (EN)
      2. 8.3.2 COMP/FSET
      3. 8.3.3 MODE / SYNC
      4. 8.3.4 Spread Spectrum Clocking (SSC)
      5. 8.3.5 Undervoltage Lockout (UVLO)
      6. 8.3.6 Power-Good Output (PG)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (PWM/PFM)
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short-Circuit Protection
      5. 8.4.5 Foldback Current Limit and Short-Circuit Protection
      6. 8.4.6 Output Discharge
      7. 8.4.7 Input Overvoltage Protection
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Programming the Output Voltage
      2. 9.1.2 External Component Selection
        1. 9.1.2.1 Inductor Selection
      3. 9.1.3 Capacitor Selection
        1. 9.1.3.1 Input Capacitor
        2. 9.1.3.2 Output Capacitor
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Fixed Output Voltage Versions
      2. 9.3.2 Synchronizing to an External Clock
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4 Device Comparison Table

DEVICE NUMBEROUTPUT
CURRENT		VOUT
DISCHARGE		FOLDBACK
CURRENT LIMIT		TYPICAL
OUTPUT CAPACITOR		SOFT
START		OUTPUT
VOLTAGE		PACKAGE TYPE
TPS628501QDRLRQ1 1AONOFF2 × 10μFInternal 1msAdjustableDRL
TPS6285010MQDYCRQ11AONOFF2 × 10μFInternal 1msFixed 1.8VDYC
TPS62850140QDYCRQ11AONON2 × 10μFInternal 1msAdjustableDYC
TPS6285018AQDRLRQ11AONOFF10μFInternal 1msFixed 1.2VDRL
TPS6285011HQDRLRQ1 1AONOFF2 × 10μFInternal 1msFixed 3.3VDRL
TPS6285010MQDRLRQ11AONOFF2 × 10μFInternal 1msFixed 1.8VDRL
TPS628501B0QDRLRQ11AONOFF2 × 10μFInternal 150µsAdjustableDRL
TPS62850120QDRLRQ11AOFFOFF2 × 10μFInternal 1msAdjustableDRL
TPS628501F0QDRLRQ11ADisconnectedOFF2 × 10μFInternal 1msAdjustableDRL
TPS628501H9QDRLRQ11ADisconnectedON2 × 10μFInternal 150µsFixed 1.15VDRL
TPS628502QDRLRQ12AONOFF2 × 10μFInternal 1msAdjustableDRL
TPS62850208QDRLRQ1

2A

ON

OFF

 2 × 10 μF Internal 1 ms Fixed 1.1V

DRL
TPS62850240QDYCRQ12AONON2 × 10μFInternal 1msAdjustableDYC
TPS62850220QDRLRQ12AOFFOFF2 × 10μFInternal 1msAdjustableDRL
TPS628502F0QDRLRQ12ADisconnectedOFF2 × 10μFInternal 1msAdjustableDRL
TPS62850240QDRLRQ12AONON2 × 10μFInternal 1msAdjustableDRL
TPS6285020MQDRLRQ12AONOFF2 × 10μFInternal 1msFixed 1.8VDRL
TPS6285021HQDRLRQ12AONOFF2 × 10μFInternal 1msFixed 3.3VDRL
TPS6285020AQDRLRQ12AONOFF2 × 10μFInternal 1msFixed 1.2VDRL
TPS628503QDRLRQ1 3AONOFF2 × 10μFInternal 1msAdjustableDRL