SLUSEN5A August   2023  – August 2026 BQ25756

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Power-On-Reset
      2. 6.3.2  Device Power-Up From Battery Without Input Source
      3. 6.3.3  Device Power Up from Input Source
        1. 6.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 6.3.3.2 REGN Regulator (REGN LDO)
        3. 6.3.3.3 Compensation-Free Buck-Boost Converter Operation
        4. 6.3.3.4 Light-Load Operation
        5. 6.3.3.5 Switching Frequency and Synchronization (FSW_SYNC)
        6. 6.3.3.6 Device HIZ Mode
      4. 6.3.4  Battery Charging Management
        1. 6.3.4.1 Autonomous Charging Cycle
          1. 6.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 6.3.4.2 Li-Ion Battery Charging Profile
        3. 6.3.4.3 LiFePO4 Battery Charging Profile
        4. 6.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 6.3.4.5 Charging Safety Timer
        6. 6.3.4.6 Thermistor Qualification
          1. 6.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 6.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 6.3.5  Power Management
        1. 6.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 6.3.5.1.1 Input Current Regulation
            1. 6.3.5.1.1.1 ILIM_HIZ Pin
          2. 6.3.5.1.2 Input Voltage Regulation
            1. 6.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
      6. 6.3.6  Reverse Mode Power Direction
      7. 6.3.7  Integrated 16-Bit ADC for Monitoring
      8. 6.3.8  Status Outputs (PG, STAT1, STAT2, and INT)
        1. 6.3.8.1 Power Good Indicator (PG)
        2. 6.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 6.3.8.3 Interrupt to Host (INT)
      9. 6.3.9  Protections
        1. 6.3.9.1 Voltage and Current Monitoring
          1. 6.3.9.1.1 VAC Over-voltage Protection (VAC_OVP)
          2. 6.3.9.1.2 VAC Under-voltage Protection (VAC_UVP)
          3. 6.3.9.1.3 Battery Over-voltage Protection (BAT_OVP)
          4. 6.3.9.1.4 Battery Over-current Protection (BAT_OCP)
          5. 6.3.9.1.5 Reverse Mode Over-voltage Protection (REV_OVP)
          6. 6.3.9.1.6 Reverse Mode Under-voltage Protection (REV_UVP)
          7. 6.3.9.1.7 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
          8. 6.3.9.1.8 REGN Under-voltage Protection (REGN_OKZ)
        2. 6.3.9.2 Thermal Shutdown (TSHUT)
      10. 6.3.10 Serial Interface
        1. 6.3.10.1 Data Validity
        2. 6.3.10.2 START and STOP Conditions
        3. 6.3.10.3 Byte Format
        4. 6.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 6.3.10.5 Target Address and Data Direction Bit
        6. 6.3.10.6 Single Write and Read
        7. 6.3.10.7 Multi-Write and Multi-Read
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host Mode and Default Mode
      2. 6.4.2 Register Bit Reset
    5. 6.5 BQ25756 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 7.2.1.2.2 Charge Voltage Selection
          3. 7.2.1.2.3 Switching Frequency Selection
          4. 7.2.1.2.4 Inductor Selection
          5. 7.2.1.2.5 Input (VAC) Capacitor
          6. 7.2.1.2.6 Output (VBAT) Capacitor
          7. 7.2.1.2.7 Sense Resistor (RAC_SNS and R BAT_SNS ) and Current Programming
          8. 7.2.1.2.8 Power MOSFETs Selection
          9. 7.2.1.2.9 Converter Fast Transient Response
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Application (USB-PD EPR Configuration)
        1. 7.2.2.1 Design Requirements
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.3.3.4 Light-Load Operation

To improve converter light-load efficiency, the device switches to Pulse Frequency Modulation (PFM) control at light load when the EN_PFM bit is set to 1. The effective switching frequency decreases accordingly when output load decreases.

EN_PFM bit is automatically cleared to 0 every time the converter starts and a valid SYNC clock input is detected on the FSW_SYNC pin, for fixed frequency operation regardless of output current. The bit can be overwritten to 1 to allow PFM after startup even when SYNC signal is present.

Light-load PFM mode can be disabled by clearing the EN_PFM bit. In this case, the device switches in PWM mode at a fixed switching frequency. It is recommended to disable PFM mode (EN_PFM = 0) when termination is enabled and set lower than 2A.