SLUSEW1C January   2024  – June 2026 TPS4810-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48100-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Circuit Breaker in Battery Management System (BMS) using Low Side Current Sense
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selection of Current Sense Resistor, RSNS
        2. 8.2.2.2 Programming the Short-Circuit Protection Threshold – RISCP Selection
        3. 8.2.2.3 Programming the Short-Circuit Protection Delay – CTMR Selection
        4. 8.2.2.4 Selection of MOSFETs, Q1 and Q2
        5. 8.2.2.5 Selection of Bootstrap Capacitor, CBST
        6. 8.2.2.6 Setting the Undervoltage Lockout
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to +150°C. V(VS) = 48V, V(BST – SRC) = 11V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VS Operating input voltage 3.5 95 V
V(S_PORR) Input supply POR threshold, rising 1.84 2.55 3.31 V
V(S_PORF) Input supply POR threshold, falling 1.7 2.33 3.06 V
I(Q) Total System Quiescent current, I(GND) V(EN/UVLO) = 2V 35 49 µA
Total System Quiescent current, I(GND)   V(EN/UVLO) =  2V, –40°C ≤ TJ ≤ +85°C 44 µA
I(SHDN) SHDN current, I(GND) V(EN/UVLO) = 0V, V(SRC) = 0V 1 4.6 µA
I(REV) I(VS) leakage current during Reverse Polarity 0V ≤ V(VS) ≤ – 65V 19 22.4 46 µA
ENABLE, UNDERVOLTAGE LOCKOUT (EN/UVLO), SHORT CIRCUIT COMPARATOR TEST (SCP_TEST) INPUT
V(UVLOR) UVLO threshold voltage, rising 1.168 1.23 1.3 V
V(UVLOF) UVLO threshold voltage, falling 1.083 1.138 1.19 V
V(ENR) Enable threshold voltage for low Iq shutdown, rising 1.03 V
V(ENF) Enable threshold voltage for low Iq shutdown, falling 0.292 V
I(EN/UVLO) Enable input leakage current V(EN/UVLO)  = 70V 626 nA
V(SCP_TEST_H) SCP test mode rising threshold 2.03 V
V(SCP_TEST_L) SCP test mode falling threshold 0.77 V
I(SCP_TEST) SCP_TEST input leakage current 90 910 nA
CHARGE PUMP (BST–SRC)
I(BST) Charge Pump Supply current V(BST – SRC)  = 10V, V(EN/UVLO) =  2V 190 345 510 µA
V(BST_UVLOR) V(BST – SRC) UVLO voltage threshold, rising V(EN/UVLO) = 2V 8 9 9.93 V
V(BST_UVLOF) V(BST – SRC) UVLO voltage threshold, falling V(EN/UVLO) = 2V 7.28 8.2 8.93 V
V(BST–SRC_ON) Charge Pump Turn ON voltage V(EN/UVLO) = 2V 9.27 10.3 11.43 V
V(BST–SRC_OFF) Charge Pump Turn OFF voltage V(EN/UVLO) = 2V 10.37 11.6 12.83 V
V(BST–SRC) Charge Pump Voltage at V(VS) = 3.5V V(EN/UVLO) = 2V 9 10.5 11.63 V
I(SRC) SRC pin leakage current V(EN/UVLO) =  2V, V(INP1) = V(INP2) = 0V 0.85 1.4 µA
GATE DRIVER OUTPUTS (G1PU, G1PD, G2)
V(G1_GOOD) G1 Good rising threshold 5.47 7 8.33 V
I(G1PU) Peak Source Current 1.62 A
I(G1PD) Peak Sink Current 2 A
I(G2) G2 Peak Source Current 1.62 A
I(G2) G2 Peak Sink Current 2 A
SHORT CIRCUIT PROTECTION (ISCP)
ISCP SCP Input Bias current 8.34 10 13.6 µA
V(SCP) SCP threshold R(ISCP) =  140.5kΩ 300 mV
R(ISCP) = 28kΩ 58.8 75 91.8 mV
R(ISCP) = 10.5kΩ 31.6 40 49.5 mV
R(ISCP) = 500Ω 14.8 20 25.3 mV
R(ISCP) =  Open 757 mV
V(SCP) SCP threshold with external bias voltage on ISCP pin V(ISCP) = 1.405V 279 300 319 mV
V(ISCP) = 280mV 67 75 83 mV
V(ISCP) = 105mV 33 40 47 mV
DELAY TIMER (TMR)
I(TMR_SRC_CB) TMR source current 67 87 114 µA
I(TMR_SRC_FLT) TMR source current 1.4 2.73 4.8 µA
I(TMR_SNK) TMR sink current 2.17 2.8 4.3 µA
V(TMR_SC) TMR trip high level threshold 0.924 1.1 1.21 V
V(TMR_LOW) TMR trip low level threshold 0.148 0.21 0.25 V
N(A-R Count) 32
INPUT CONTROLS (INP1, INP2), CURRENT SENSE SELECT (CS_SEL) and FAULT FLAG (FLT) 
R(FLT) FLT Pull-down resistance 52 83 110 Ω
I(FLT) FLT Input leakage current 0V ≤ V(FLT) ≤ 20V 530 nA
V(INP1_H),  V(INP2_H)  INP high level threshold 2.02 V
V(INP1_L), V(INP2_L)   INP low level threshold 0.787 V
I(INP1), I(INP2) INP Input leakage current 98 240 nA
V(CS_SEL_H)  CS_SEL threshold for low side sensing 2.06 V
V(CS_SEL_L)  CS_SEL threshold for high side sensing 0.786 V