SLUSFG5A November   2024  – September 2025 UCC33421-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Insulation Characteristics Curves
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 Output Voltage Soft-Start
      3. 7.3.3 Output Voltage Steady-State Regulation
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Input Under-Voltage and Over-Voltage Lockout
        2. 7.3.4.2 Output Under-Voltage Protection
        3. 7.3.4.3 Output Over-Voltage Protection
        4. 7.3.4.4 Over-Temperature Protection
        5. 7.3.4.5 Fault Reporting and Auto-Restart
      5. 7.3.5 VCC Load Recommended Operating Area
      6. 7.3.6 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical and Packaging Information

8.2.2 Detailed Design Procedure

The UCC33421-Q1 design procedure is very simple, the device requires two decoupling capacitors connected between VINP and GNDP pins for the input supply, and two decoupling capacitors for the isolated output supply placed between VCC and GNDS pins to form a completely functinoal DC/DC converter.

A low ESR, ESL ceramic capacitors are recommended to be connected close to the device pins. It should be noted that the effective burst frequency would be impacted by the selected VCC output capacitor