The UCC12050EVM-022 board layout is optimized for EMI performance. One EMI mitigation technique demonstrated is an interlayer stitching capacitor (shown as C5 in the schematic). The GNDP and GNDS planes on the inner layers (layer 2 and layer 3) are overlapped in order to form a common-mode, capacitive filter between the two ground planes. GNDP on layer 2 and GNDS on layer 3 overlap. Note that the GND planes do not go all the way to the edge of the board where they overlap. This is to illustrate how to satisfy isolation requirements. There is sufficient distance between the edge of the overlapping layers using this methodology. This only must be used when the planes overlap close to the edge of the board. The second EMI mitigation technique used is the use of stitch vias in the GND planes (GNDP and GNDS) to further suppress EM transmissions.