SLUUCC6A September   2020  – April 2021 TPS563211


  1. 1Introduction
  2. 2Performance Specification Summary
  3. 3Modifications
  4. 4Test Setup
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
  5. 5Board Layout
    1. 5.1 Layout
    2. 5.2 EVM Picture
  6. 6Schematic, List of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 List of Materials
  7. 7Reference
  8. 8Revision History


The board layout for the TPS563211EVM is shown in Figure 5-1, Figure 5-2, and Figure 5-3. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS563211 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C1, C2, and C3 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the point of regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2-oz copper thickness.

GUID-20200915-CA0I-HJ2F-LGVH-61KGXFCFKLPF-low.gifFigure 5-1 TPS563211EVM Top Assembly
GUID-20200915-CA0I-QTD9-RXWQ-0QD3XXPMLBLQ-low.gifFigure 5-2 TPS563211EVM Top Layer
GUID-20200915-CA0I-KQ7L-WDHM-VWR0S4DG1SH6-low.gifFigure 5-3 TPS563211EVM Bottom Layer