SLUUCD1A April   2020  – April 2022 TPS62860

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification
    3. 1.3 Modifications
      1. 1.3.1 IC U1 Operation
  3. 2Setup
    1. 2.1 Input and Output Connector Description
      1. 2.1.1  J1, Pin 1 and 2 – VIN
      2. 2.1.2  J1, Pin 3 and 4 – S+/S-
      3. 2.1.3  J1, Pin 5 and 6 – GND
      4. 2.1.4  J2, Pin 1 and 2 – VOUT
      5. 2.1.5  J2, Pin 3 and 4 – S+/S-
      6. 2.1.6  J2, Pin 5 and 6 – GND
      7. 2.1.7  JP1 – EN
      8. 2.1.8  JP3 – VSEL1
      9. 2.1.9  JP4 - VSEL2
      10. 2.1.10 JP5 – PG
    2. 2.2 Setup
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

3.1 Layout

Figure 3-1 through Figure 3-5 show the component placement and PCB layout of the TPS6286x1EVM.

Figure 3-1 TPS6286x1EVM PCB - Assembly Layer
Figure 3-2 TPS6286x1EVM PCB - Top Layer
Figure 3-3 TPS6286x1EVM PCB - Signal Layer 1 (Top View)
Figure 3-4 TPS6286x1EVM PCB - Signal Layer 2 (Top View)
Figure 3-5 TPS6286x1EVM PCB - Bottom Layer (Top View)
GUID-0AE439AC-2E4C-4931-82B7-5B99082C95AF-low.pngFigure 3-6 TPS628601EVM Angled View
GUID-4E59237B-357B-406C-A406-A227E72F9A92-low.jpgFigure 3-7 TPS628601EVM Overhead View