SLUUCS6A february   2023  – august 2023 UCC14340-Q1 , UCC14341-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 U1 Component Selection
    2. 1.2 Pin Configuration and Functions
  5. 2Description
    1. 2.1 EVM Electrical Performance Specifications
  6. 3Schematic
  7. 4EVM Setup and Operation
    1. 4.1 Recommended Test Equipment
    2. 4.2 External Connections for Easy Evaluation
    3. 4.3 Powering the EVM
      1. 4.3.1 Power on for Start-up
      2. 4.3.2 Power off for Shutdown
    4. 4.4 EVM Test Points
    5. 4.5 Probing the EVM
  8. 5 Performance Data
    1. 5.1  Efficiency Data
    2. 5.2  Regulation Data
    3. 5.3  Steady State Input Current
    4. 5.4  Start-up Waveforms
    5. 5.5  Inrush Current
    6. 5.6  AC Ripple Voltage
    7. 5.7  EN-to-/PG Timing
    8. 5.8  RLIM
    9. 5.9  Fault Protection
      1. 5.9.1 Output UVLO
      2. 5.9.2 Output OVP of COM-VEE
    10. 5.10 Shutdown
    11. 5.11 Thermal Performance
  9. 6Assembly and Printed Circuit Board (PCB) Layers
  10. 7Bill of Materials (BOM)
  11. 8Revision History

2.1 EVM Electrical Performance Specifications

Table 2-1 EVM Electrical Specifications VIN = 15 V, VDD=VDD-VEE = 18 V, VEE=VEE-COM = -4 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN Input voltage range PVDD-VEE=1.5 W 13.5 15 16.5 V
VIN_ON Input voltage on PVDD-VEE=0 W 12 12.5 V
VIN_OFF Input voltage off PVDD-VEE=0 W 11 11.5 V
IIN_FL Input current at full load VIN = 13.5 V, IVDD = 68 mA 230 mA
VIN = 15 V, IVDD = 68 mA 210
VIN = 16.5 V, IVDD = 68 mA 200
IIN_NL Input current at no load VIN = 13.5 V, IVDD =IVEE = 0 mA 33 mA
VIN = 15 V, IVDD =IVEE = 0 mA 30
VIN = 16.5 V, IVDD =IVEE = 0 mA 29
IIN_OFF Input current at EN LOW EN LOW, VDD = VEE = 0 V 570 650 µA
EN to /PG delay IVDD =IVEE = 0 mA 4 5 ms
OUTPUT CHARACTERISTICS
VDD-VEE DC full load set-point 13.5 V<VIN<16.5 V, IVDD = 68 mA 21.5 22.0 22.5 V
IVDD VDD load current range 13.5 V < VIN < 16.5 V 0 68 mA
VDD%LD Load regulation V D D R E G = V I ( m i n ) - V I ( m a x ) V I ( m a x ) × 100 %

VIN=15 V, 0 mA ≤ IVDD ≤ 68 mA

 0.5 %
VDD%LN Line regulation V D D R E G = V I ( m i n ) - V I ( m a x ) V I ( m a x ) × 100 %

IVDD=68 mA, 13.5 V ≤ VIN ≤ 16.5 V

 0.05 %
VDDAC pk-to-pk AC ripple IVDD = 68 mA 290 320 mV
VDDSS Soft-start IVDD = IVEE = 0 mA 1.8 ms
PMAX Maximum output power IVDD(TYP) = 68 mA, IVDD(MAX) = 91 mA 1.5 2 W
VEE-COM DC full load set-point 13.5 V ≤ VIN ≤ 16.5 V, IVEE = 30 mA -3.992 -4.008 V
IVEE VEE load current range 13.5 V≤ VIN ≤ 16.5 V 0 35 mA
VEEAC pk-to-pk AC ripple IVEE = 30 mA 110 120 mV
SYSTEM CHARACTERISTICS
η100% Full load efficiency IVDD = 68 mA 48 %
η50% Half load efficiency IVDD = 34 mA 43 %
FSW Switching frequency (1) VIN = 13.5 V, 0 mA < IVDD < 68 mA 18 MHz
VIN = 15 V, 0 mA < IVDD < 68 mA 15
VIN = 16.5 V, 0 mA < IVDD < 68 mA 12
VDD(OCL) VDD overcurrent limit IVDD > 110 mA 130 135 mA
VEE(OCL) VEE overcurrent limit IVEE > 30 mA 35 42 mA
TMAX Maximum temperature rise above ambient IVDD = 68 mA 44 50 °C
(1) Switching frequency is specified as primary-side switching frequency. Secondary-side is 2x primary