SLUUCT9 September   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 General TI High Voltage Evaluation User Safety Guidelines
  6. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Header Information
    3. 2.3 Jumper Information
    4. 2.4 Connectors Information
    5. 2.5 Interfaces Information
    6. 2.6 Test Points
  7. 3Implementation Results
    1. 3.1 Evaluation Setup
    2. 3.2 Performance Data and Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)

2.6 Test Points

Table 2-6 Test Point Description
Test Point Test Point Board Marker Description
TP1 VBIAS/VCC1 EN for UCC14240
TP2 INA Input for channel A
TP3 INB Input for channel B
TP4 VDDA Output side channel A supply
TP5 GND Input side ground
TP6 GND Input side ground
TP7 GND Input side ground
TP8 VSSA Output side channel A ground
TP9 VSSB Output side channel B ground
TP11 XEN Test point to apply an external enable signal
TP12 PG Fault pin for detecting fault status for UCC14240
TP15 ENA Test point for measuring UCC14240 enable signal
TP16 VDDB Output side channel B supply
TP17 VIN Test point for primary supply for UCC14240 (21V-27V)
TP18 GND Input side ground
TP19 VGA Q1 FET gate
TP21 VGB Q2 FET gate
J1 VIN MMCX pad for primary supply for UCC14240 (21V-27V)
J2 VDDA MMCX pad for output side channel A supply
J3 OUTA MMCX pad for channel A output
J4 VGA MMCX pad for Q1 gate
J6 DT MMCX pad for Deadtime pin
J10 INA MMCX pad for input to channel A
J11 INB MMCX pad for input to channel B
J13 VDDB MMCX pad for output side channel B supply
J14 OUTB MMCX pad for channel B output
J15 VGB MMCX pad for Q2 gate
J19 VDDB MMCX pad for output low side supply