SLUUDF7 User guide

SLUUDF7 January 2026 LMK3H2104

1.1 LMK3H2104A09 Configuration Information

Table 1-1 LMK3H2104A09 Frequency Configuration

OTP Page	OUT0 (MHz)	OUT1 (MHz)	OUT2 (MHz)	OUT3 (MHz)	REF0 (MHz)	REF1 (MHz)
OTP Page 0	50	50	25	24	50	50
OTP Page 1	50	50	25	24	50	50
OTP Page 2	50	50	25	24	50	50
OTP Page 3	50	50	25	24	50	50

Table 1-2 LMK3H2104A09 I2C Configuration

OTP Page	I2C Configuration
OTP Page 0	I2C Addres: 0X68 1 Byte Register Addressing
OTP Page 1	I2C Addres: 0X68 1 Byte Register Addressing
OTP Page 2	I2C Addres: 0X68 1 Byte Register Addressing
OTP Page 3	I2C Addres: 0X68 1 Byte Register Addressing

Table 1-3 LMK3H2104A09 GPI Settings, OTP Page 0

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Normal	Enabled	Disabled
GPI1	GPI	Normal	Enabled	Disabled
GPI2	Alternate OE, Alternate Mapping 1	Normal	Enabled	Disabled

Table 1-4 LMK3H2104A09 GPIO Settings, OTP Page 0

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Alternate OE, Alternate Mapping 1	Normal	Disabled	Enabled
GPIO1	GPI	Normal	Enabled	Disabled

Table 1-5 LMK3H2104A09 Input Settings, OTP Page 0

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Power Down	N/A (IN0 Unused)	None, DC

Table 1-6 LMK3H2104A09 Output Settings, OTP Page 0

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	50	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT1	50	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT2	25	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT3	24	In-Phase LVCMOS	PATH0	Enabled	No OE Group	Disabled
REF0	50	N/A	PATH1	Enabled	No OE Group	Disabled
REF1	50	N/A	PATH1	Enabled	No OE Group	Disabled

Table 1-7 LMK3H2104A09 GPI Settings, OTP Page 1

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Normal	Enabled	Disabled
GPI1	GPI	Normal	Enabled	Disabled
GPI2	Alternate OE, Alternate Mapping 1	Normal	Enabled	Disabled

Table 1-8 LMK3H2104A09 GPIO Settings, OTP Page 1

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Alternate OE, Alternate Mapping 1	Normal	Disabled	Enabled
GPIO1	GPI	Normal	Enabled	Disabled

Table 1-9 LMK3H2104A09 Input Settings, OTP Page 1

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Power Down	N/A (IN0 Unused)	None, DC

Table 1-10 LMK3H2104A09 Output Settings, OTP Page 1

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	50	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT1	50	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT2	25	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT3	24	In-Phase LVCMOS	PATH0	Enabled	No OE Group	Disabled
REF0	50	N/A	PATH1	Enabled	No OE Group	Disabled
REF1	50	N/A	PATH1	Enabled	No OE Group	Disabled

Table 1-11 LMK3H2104A09 GPI Settings, OTP Page 2

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Normal	Enabled	Disabled
GPI1	GPI	Normal	Enabled	Disabled
GPI2	Alternate OE, Alternate Mapping 1	Normal	Enabled	Disabled

Table 1-12 LMK3H2104A09 GPIO Settings, OTP Page 2

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Alternate OE, Alternate Mapping 1	Normal	Disabled	Enabled
GPIO1	GPI	Normal	Enabled	Disabled

Table 1-13 LMK3H2104A09 Input Settings, OTP Page 2

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Power Down	N/A (IN0 Unused)	None, DC

Table 1-14 LMK3H2104A09 Output Settings, OTP Page 2

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	50	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT1	50	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT2	25	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT3	24	In-Phase LVCMOS	PATH0	Enabled	No OE Group	Disabled
REF0	50	N/A	PATH1	Enabled	No OE Group	Disabled
REF1	50	N/A	PATH1	Enabled	No OE Group	Disabled

Table 1-15 LMK3H2104A09 GPI Settings, OTP Page 3

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Normal	Enabled	Disabled
GPI1	GPI	Normal	Enabled	Disabled
GPI2	Alternate OE, Alternate Mapping 1	Normal	Enabled	Disabled

Table 1-16 LMK3H2104A09 GPIO Settings, OTP Page 3

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Alternate OE, Alternate Mapping 1	Normal	Disabled	Enabled
GPIO1	GPI	Normal	Enabled	Disabled

Table 1-17 LMK3H2104A09 Input Settings, OTP Page 3

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Power Down	N/A (IN0 Unused)	None, DC

Table 1-18 LMK3H2104A09 Output Settings, OTP Page 3

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	50	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT1	50	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT2	25	In-Phase LVCMOS	PATH1	Enabled	No OE Group	Disabled
OUT3	24	In-Phase LVCMOS	PATH0	Enabled	No OE Group	Disabled
REF0	50	N/A	PATH1	Enabled	No OE Group	Disabled
REF1	50	N/A	PATH1	Enabled	No OE Group	Disabled