SLUUDJ9 September   2026 LMK3H2104

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1Configuration Overview
    1. 1.1 LMK3H2104 Configuration Information
  4. 2Device Register Map
  5. 3Device Registers
  6. 4Revision History

1.1 LMK3H2104 Configuration Information

Table 1-1 Frequency Configuration
OTP PageOUT0 (MHz)OUT1 (MHz)OUT2 (MHz)OUT3 (MHz)REF0 (MHz)REF1 (MHz)
OTP Page 01001001001002525
OTP Page 11001001001002525
OTP Page 21001001001002525
OTP Page 31001001001002525
Table 1-2 I2C Configuration
OTP PageI2C Configuration
OTP Page 0

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 1

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 2

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 3

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 0

Table 1-3 GPI Settings, OTP Page 0
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0Group OE, OE_GROUP_0InvertedEnabledDisabled
GPI1Group OE, OE_GROUP_1InvertedEnabledDisabled
GPI2Group OE, OE_GROUP_2InvertedEnabledDisabled
Table 1-4 GPIO Settings, OTP Page 0
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0Group OE, OE_GROUP_3InvertedEnabledDisabled
GPIO1Status Output, CLK_READYNormalEnabledDisabled
Table 1-5 Input Settings, OTP Page 0
InputPowered Up/DownInput FormatInput Termination
IN_0Powered DownN/A (IN0 Unused)None, DC
Table 1-6 Output Settings, OTP Page 0
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0100100 Ω LP-HCSLPATH1EnabledOE_GROUP_0Disabled
OUT1100100 Ω LP-HCSLPATH1EnabledOE_GROUP_1Disabled
OUT2100100 Ω LP-HCSLPATH1EnabledOE_GROUP_2Disabled
OUT3100100 Ω LP-HCSLPATH1EnabledOE_GROUP_3Disabled
REF025N/APATH1DisabledNo OE GroupDisabled
REF125N/APATH1DisabledNo OE GroupDisabled

OTP Page 1

Table 1-7 GPI Settings, OTP Page 1
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0Group OE, OE_GROUP_0InvertedEnabledDisabled
GPI1Group OE, OE_GROUP_1InvertedEnabledDisabled
GPI2Group OE, OE_GROUP_2InvertedEnabledDisabled
Table 1-8 GPIO Settings, OTP Page 1
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0Group OE, OE_GROUP_3InvertedEnabledDisabled
GPIO1Status Output, CLK_READYNormalEnabledDisabled
Table 1-9 Input Settings, OTP Page 1
InputPowered Up/DownInput FormatInput Termination
IN_0Powered DownN/A (IN0 Unused)None, DC
Table 1-10 Output Settings, OTP Page 1
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0100100 Ω LP-HCSLPATH1EnabledOE_GROUP_0Enabled, -0.1% Down-spread
OUT1100100 Ω LP-HCSLPATH1EnabledOE_GROUP_1Enabled, -0.1% Down-spread
OUT2100100 Ω LP-HCSLPATH1EnabledOE_GROUP_2Enabled, -0.1% Down-spread
OUT3100100 Ω LP-HCSLPATH1EnabledOE_GROUP_3Enabled, -0.1% Down-spread
REF025N/APATH1DisabledNo OE GroupEnabled, -0.1% Down-spread
REF125N/APATH1DisabledNo OE GroupEnabled, -0.1% Down-spread

OTP Page 2

Table 1-11 GPI Settings, OTP Page 2
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0Group OE, OE_GROUP_0InvertedEnabledDisabled
GPI1Group OE, OE_GROUP_1InvertedEnabledDisabled
GPI2Group OE, OE_GROUP_2InvertedEnabledDisabled
Table 1-12 GPIO Settings, OTP Page 2
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0Group OE, OE_GROUP_3InvertedEnabledDisabled
GPIO1Status Output, CLK_READYNormalEnabledDisabled
Table 1-13 Input Settings, OTP Page 2
InputPowered Up/DownInput FormatInput Termination
IN_0Powered DownN/A (IN0 Unused)None, DC
Table 1-14 Output Settings, OTP Page 2
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0100100 Ω LP-HCSLPATH1EnabledOE_GROUP_0Enabled, -0.3% Down-spread
OUT1100100 Ω LP-HCSLPATH1EnabledOE_GROUP_1Enabled, -0.3% Down-spread
OUT2100100 Ω LP-HCSLPATH1EnabledOE_GROUP_2Enabled, -0.3% Down-spread
OUT3100100 Ω LP-HCSLPATH1EnabledOE_GROUP_3Enabled, -0.3% Down-spread
REF025N/APATH1DisabledNo OE GroupEnabled, -0.3% Down-spread
REF125N/APATH1DisabledNo OE GroupEnabled, -0.3% Down-spread

OTP Page 3

Table 1-15 GPI Settings, OTP Page 3
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0Group OE, OE_GROUP_0InvertedEnabledDisabled
GPI1Group OE, OE_GROUP_1InvertedEnabledDisabled
GPI2Group OE, OE_GROUP_2InvertedEnabledDisabled
Table 1-16 GPIO Settings, OTP Page 3
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0Group OE, OE_GROUP_3InvertedEnabledDisabled
GPIO1Status Output, CLK_READYNormalEnabledDisabled
Table 1-17 Input Settings, OTP Page 3
InputPowered Up/DownInput FormatInput Termination
IN_0Powered DownN/A (IN0 Unused)None, DC
Table 1-18 Output Settings, OTP Page 3
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0100100 Ω LP-HCSLPATH1EnabledOE_GROUP_0Enabled, -0.5% Down-spread
OUT1100100 Ω LP-HCSLPATH1EnabledOE_GROUP_1Enabled, -0.5% Down-spread
OUT2100100 Ω LP-HCSLPATH1EnabledOE_GROUP_2Enabled, -0.5% Down-spread
OUT3100100 Ω LP-HCSLPATH1EnabledOE_GROUP_3Enabled, -0.5% Down-spread
REF025N/APATH1DisabledNo OE GroupEnabled, -0.5% Down-spread
REF125N/APATH1DisabledNo OE GroupEnabled, -0.5% Down-spread