Figure 3-1 Solution for Fault Glitch

Adding the RC filter between the Fault and MCU to eliminate the glitch.

Since point B from Figure 2-1 is in unknown status until V_IN reaches UVLO (4 V, the worst case in TPS2065D or TPS2069D). The worst case for Fault low is from V_in = V_th to V_in reach UVLO.

If V_in = 5 V, and V_IN ramp = V_ramp V/ms, the worst Fault low period T_{FAULT_L} = (UVLO - V_th) / V_ramp. You need Fault_A to be > V_{FAULT_H} (1.7 V) during T_{FAULT_L}. V_{FAULTd_H} according to the customer's definition. Before power on, the initial voltage on C1 is 3.3 V. Before V_in reaches the UVLO voltage threshold, the voltage on C1 discharges through the FLT pin to GND.

Select RC value to make sure:

Equation 1.

If V_ramp = 5 V/ms, then T_{FAULT_L} = 0.6 ms, select R = 1kΩ, C=1 µF.

Figure 3-2 Without RC Filter Waveform, 5 V/ms

Figure 3-3 With RC Filter Waveform, 5 V/ms

As seen in Figure 3-2, without the RC filter added, the Fault pin is pulled down to 0 V. The duration time depends on the slew rate of input. Figure 3-3 displays that with the RC filter added, although the Fault pin has a glitch, the terminal Fault_A that is connected to MCU almost has no glitches, always high level. The method proposed can eliminate the fault glitch concern.