2 Proposed Circuit Principle

The proposed solution utilizes a special feature of the EN logic threshold voltage, as shown in Table 2-1:

• When V_IN > 1.8 V or V_OUT > 2.2 V, the EN logic high threshold V_{EN_H} is 1.2 V.
• After the device starts to operate, the typical EN logic low threshold V_{EN_L} is typically 0.42 V, with a minimum of 0.35 V and a maximum of 0.42 V

Figure 2-1 shows a simplified schematic of the proposed solution. The operating principle details follow:

• At the beginning, the device V_IN < 1.7 V and V_OUT = 0 V. The device shuts down and disconnects VIN and VOUT. The NMOS Q1 turns off and the voltage at EN pin V_EN is equal to V_IN.
• When V_IN increases to higher than a typical 1.7 V (maximum 1.8 V) and EN voltage is higher than the logic high threshold, the device starts to operate. The EN logic high threshold is typically 0.95 V with a maximum value of 1.2 V. As V_EN = V_IN > 1.7 V, the device begins the soft-start process. During the soft-start process, the device initially pre-charges the V_OUT closed to V_IN, then switches to boost the output to the higher voltage.
• After the V_OUT becomes higher than 2.2 V, the UVLO value of the VIN pin is changed to typical 0.4 V and the EN logic low threshold is changed to 0.42 V. Because of the R5, R6, and C2, the Q1 gate voltage is still too low to turn on, the V_EN is still equal to V_IN.
• After the V_OUT ramps to the setting value and Q1 turns on, the voltage at the EN pin is defined by Equation 1.
  Equation 1.
• If VIN declines and results in V_EN lower than typical 0.42 V, the device shuts down. The V_OUT is discharged by the loading. After Q1 turns off, V_EN will be equal to VIN again. However, the device would keep off if V_IN < 1.7 V.

Figure 2-1 Schematic of the Proposed Circuit

Based on the previous analysis , the UVLO value set by this method must be lower than 1.7 V.

The function of the R5, R6, and C2 is to keep Q1 off before the VOUT is ready. But Q1 must turn on after the output voltage is stable at the setting voltage. The gate-to-source voltage at stable condition is defined by Equation 2, which should be 10% higher than the MOSFET gate to source threshold voltage for design margin.

Equation 2.

where

• V_GS(th) is the gate-to-source threshold voltage of a MOSFET
• V_OUT is the setting value of the output voltage

The time constant of the R5, R6, and C2, which is defined by Equation 3, is suggested to be the startup time of the device – 700 µs (typical).

Equation 3.

Figure 2-2 shows the method to shut down the boost converter through an external control logic pin. The device shuts down if CTRL is high, while the device is controlled by the proposed circuit if CTRL is low. If the CTRL signal can support open-drain output, it can connect to the EN pin directly. Then the boost is off at CTRL low logic, and it is controlled by the proposed circuit at CTRL open-drain.

Figure 2-2 Method to Shutdown Proposed Circuit With I/O

Assuming the output voltage is set to 5 V and the new UVLO voltage is 1.2 V, the following process details the design of the components for the proposed circuit:

• Set R3 to be 1 MΩ, R4 will be 538 kΩ based on Equation 1. Considering the threshold variation in Table 2-1, the new UVLO value would have a 1-V minimum and 1.29-V maximum.
• Select CSD13381F4 as the Q1, which has a typical 0.85-V gate-to-source threshold voltage V_GS(th) with a 0.65-V minimum and 1.1-V maximum at room temperature. Considering the variation of V_GS(th) overtemperature, the gate-to-source voltage must be higher than 1.2 V to safely turn on the MOSFET. Select 1-MΩ R5, the R6 would be 359 kΩ according to Equation 2.
• Select the time constant of the R5, R6, and C2 to be 700-µs (TPS61022 start up time), the C2 would be 2.6 nF from Equation 3.

Figure 2-3 shows the value of the external components.

Figure 2-3 Components Value of the Proposed Circuit