As shown in Figure 2-1, cascaded devices compose one data stream (SIN1, SIN2…,SINx). The SCLK frequency is determined by the data volume of the data stream in each frame and frame rate. Each scan line of TLC6983 has 48-bit-wide memory for every corresponding RGB channel. If dual devices are in stackable mode (N_stack = 2), there are 32 channels for each sub-block. If three devices are in stackable mode (N_stack = 3), there are 48 channels for each sub-block.

Note that if there are unused channels in the sub-block, the FPGA controller still needs to send zero gray scale data (GS data) to the unused channels since the GS data needs to be continuously stored into the SRAM for all 16 RGB channels in each scan line. The channel counter resets to 0 after 16 gray scale data-write operations. However, there is no need to send the zero data to unused scan lines since all scan lines have been updated with new gray scale data once the line counter exceeds the scan line number.

The equation of the data volume is,

In this example, the data volume V_Data = 18 × 16 × 48 × 6 = 82.944Kb.

For the data transmission, with the exception of the effective gray scale data, there is other data. Some of the other data is head bytes, a check bit, end bits, and more. The data transmission efficiency is supposed to be 80% based on empirical value.

Hence, the equation of the minimum SCLK frequency with single-edge transmission is,

In this example, the minimum SCLK frequency is 12.4 MHz with single-edge transmission and 6.2 MHz with dual-edge transmission. Finally, single-edge transmission of 12.5-MHz SCLK can be selected, which is generally used in an FPGA.

Table 2-2 lists the updated design requirements based on above calculations. Then engineers can start the configuration work for the driver registers to match those requirements.