Vmain from the power switches is used to drive the POL converters which provide the POLA, POLB, POLC, POLD, POLE, and POLF output voltage to the KU060. For a Xilinx KU060 FPGA, these correspond to VCOREA0.95V, VCOREB0.95V, MGT1.0V, MGT1.2V, IO1.8V, and IO3.3V power rails respectively. Two TPS7H4001-SP regulators provide the core rail supply (POLA, POLB), and four TPS50601A-SP regulators are used for POLC, POLD, POLE, and POLF. The output from each POL converter is passed to the connector on the power-supply board, which is used to provide power to the FPGA and other boards. VCOREA0.95V and VCOREB0.95V are connected together for the Xilinx KU060 FPGA used in STAR-Tiger.

A voltage sense signal is also provided for each POL converter on another connector. Each sense signal is connected close to the load on the FPGA board and senses the voltage at the load, so that each POL can adjust the voltage to the required level.

Each POL converter has an output undervoltage and overvoltage detection circuit which checks that the output voltage is within 94 – 106% (typical), 97 – 103% (worst-case) of the nominal value. If this voltage goes outside 91 – 109% (typical), 90 – 110% (worst-case) of the nominal value, the power good (PG) pin of that device is de-asserted pulling the corresponding PGx signal low which propagates through a chain of POL converters causing PGPOLx(H) to be de-asserted. A separate overvoltage detection circuit is used to improve accuracy of the overvoltage threshold.

Each POL converter is enabled by an EN input and indicates when the output has reached, or is close to, the required output voltage by asserting an open-drain power good signal. The POL converters are grouped into three groups:

• POLA, POLB, and POLC (KU060 VCOREA0.95V, VCOREB0.95V, and MGT1.0V, respectively)
• POLD and POLE (KU060 MGT1.2V and IO1.8V, respectively)
• POLF (KU060 IO3.3V)

POLs in a group are enabled by the same enable signal and generate PG only when all the POLs in the group have reached close to their nominal output voltage. The groups are arranged as follows:

• Group A enabled by ENA, generating PGA: POLA, POLB, and POLC
• Group B enabled by ENB, generating PGB: POLD, POLE
• Group C enabled by ENC, generating PGC: POLF

Table 2-1 shows a summary of the KU060 power rails used in the SpaceFibre switch, the maximum current capability, dynamic load, and voltage transient for which the rails were designed.

POLF was configured to 3.218 V (instead of 3.3 V) to allow sufficient margin between the operating maximum voltage and the absolute maximum voltage rating of the KU060. The operating maximum voltage includes regulation and overvoltage detection requirements across all conditions.