3 Thermally Enhanced Package

For cooling through the top side of the package, heat sinks are commonly used to transfer heat out of IC packages into the ambient environment. Board designs, especially ones that include resource-intensive computing chipsets, will often have a heat sink covering the entire board in order to maximize surface area exposure to a fluid medium. The fluid medium could either be ambient static air, ambient airflow, or a liquid medium such as water, refrigerants, or oil. Figure 3-1 shows a visual diagram of component placement.

A thermal paste is applied to the top of the device to evenly coat the conduction surface, then the heat sink is attached to maximize surface area for heat dissipation. Since most power management ICs are over-molded with a mold compound, package technology needs slight adjustments to optimized heat transfer to the heat sink.

Thermally Enhanced Package (TEP) technology exposes the inner silicon die on the top side of the package in order to have direct contact with a thermal paste and heat sink, enabling better heat conduction through the top side of the package. TEP is formed using a selective "film assist" mold process in which a thin film is used during the molding process to prevent mold flow over the die. The process flow is almost identical to the standard over-mold process, with the exception that the top side mold compound is left out in order to expose the silicon. Figure 3-2 shows a photo of TPS543B25T, a buck converter in a TEP, from the top side of the TPS543B25TEVM.

With the top side mold compound removed, the θ_Jc(top) of TPS543B25T is 0.2°C/W, a 0.6°C/W reduction from the over-molded version of the same device, TPS543B25. This yields a reduction in overall thermal resistance when a heat sink is applied, as shown in Table 3-1.

A device with TEP with a heat sink can lower thermal resistance by approximately 2.1°C/W compared to a device with standard packaging without a heat sink. If airflow is applied, thermal resistance is reduced by a further 3.2°C/W.

When the device is under load, a lower thermal resistance yields a significant reduction in temperature rise, especially at higher current. Figure 3-3 shows the junction temperature (T_J) of TPS543B25T and TPS543B25 across load at 80°C ambient temperature (T_A). Both were tested on the TPS543B25EVM. Temperature rise was approximated by multiplying the measured power loss on the PG diode by the thermal resistance. T_J was calculated by adding the temperature rise to the 80°C T_A. Note that the rated maximum junction temperature for both TPS543B25 and TPS543B25T is 150°C.

The T_J of TPS543B25T with a heat sink applied is 13.7°C cooler than TPS543B25 at full load, and can be cooled by an additional 20.8°C with air flow.