While optimizing PCB layout has the greatest influence on overall system heat dissipation, the package of the IC itself must be carefully selected as well in order to optimize heat dissipation. The lead frame construction within the package can have significant influence in getting heat out of the silicon die and into the PCB and its surrounding environment.

Recent advancements in packaging technology have enabled the dissipation of heat from the package much more efficiently. In traditional wire bond QFN packaging shown in Figure 2-2, the bond wires that connect the silicon die to the outer pins add resistances that contribute to additional conduction loss. This conduction loss produces heat within the package that does not dissipate heat optimally out of the package, due to limited contact with the PCB.

HotRod™ QFN packaging, shown in Figure 2-3, flips the chip and places the pins directly onto the lead frame using copper posts and gold or tin solder. This eliminates the need for bond wires, which decreases conduction loss and increases conductor contact with the PCB. However, pin-out design in a single layer lead frame can often limit the ground pad size, lowering the area of heat conduction within the package.

In order to enable more flexible pinout design, Routable lead frame QFN, the latest packaging technology, separates the lead frame into three layers of substrate with inner-layer trace connections, as shown in Figure 2-4. This enables most devices with this package to be designed with the maximum ground pad area on the bottom-most layer of the lead frame, allowing even better heat conduction contact with the PCB.