SLVAG35 August 2026 BQ78702B , BQ78706 , BQ79718B-Q1 , BQ79731-Q1 , BQ79731B-Q1
Figure 1-1 shows the I2C application block diagram from the BQ79718 datasheet; this architecture is also applicable to BQ78706 and BQ79731. Each AFE in the daisy chain can connect to multiple I2C slave nodes.
Figure 1-1 BQ797xx I2C Application DiagramI2C data transmission and reception mainly rely on the I2C_CTRL, I2C_WR_DATA, and I2C_RD_DATA registers, prior to which GPIO functional configuration (I2C enable) must be completed. The MCU writes data into the AFE register I2C_WR_DATA via the daisy chain, and the read-back data is stored in I2C_RD_DATA. I2C_CTRL configures SEND, RECEIVE, START, STOP, NACK, and initiates I2C communication.
Figure 1-2 AFE and BJB I2C Related RegistersI2C_WR_DATA: Stores data to be written into the EEPROM.
I2C_RD_DATA: Stores data read from the EEPROM.
I2C_CTRL: START, NACK, and STOP before and after data in the I2C protocol are configured through this register. It also defines whether the current communication is transmit or receive, and initiates I2C communication.
Figure 1-3 I2C_CTRL Register DefinitionThe host node (AFE or BJB) controls START and STOP to inform the EEPROM of communication start and end.
After receiving 8bit data, the slave node (EEPROM) pulls SDA low for 1bit (ACK) to inform the host that data reception is complete and the next byte can be sent.
Figure 1-4 Mapping Between I2C Communication Protocol and RegistersFor detailed I2C communication protocols, please refer to the application report Understanding the I2C Bus.
The EEPROM read communication process is divided into the following 7 steps:
Figure 1-5 7-Step Flowchart of I2C EEPROM Read Communication