SLVK183 February 2025 TPS7H6005-SP , TPS7H6015-SP , TPS7H6025-SP
The TPS7H60x5-SP is fabricated in the TI Linear BiCMOS 250nm process with a 4LM back-end-of-line (BEOL) stack. The total stack height from the surface of the passivation to the silicon surface is 9.8μm based on nominal layer thickness as shown in Figure 5-1. Accounting for energy loss through the 1mil thick Aramica beam port window, the 40mm air gap, and the BEOL stack over the TPS7H60x5-SP, the effective LET (LETEFF) at the surface of the silicon substrate and the depth was determined with the SEUSS 2020 Software (provided by the Texas A&M Cyclotron Institute and based on the latest SRIM-2013 [7] models). The results are shown in Table 5-1.
| Ion Type | Beam Energy (MeV / nucleon) | Angle of Incidence | Degrader Steps (Number) | Degrader Angle | Range in Silicon (µm) | LETEFF (MeV × cm2/ mg) |
|---|---|---|---|---|---|---|
| 109Ag | 15 | 0 | 0 | 0 | 95.1 | 48 |
15 | 31.5 | 0 | 0 | 72.2 | 58 | |
| 165Ho | 15 | 0 | 0 | 0 | 97.2 | 75 |