SLVS752D November   2007  – April 2026 TPS5420-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information 
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Oscillator Frequency
      2. 6.3.2  Voltage Reference
      3. 6.3.3  Enable (ENA) and Internal Slow Start
      4. 6.3.4  Undervoltage Lockout (UVLO)
      5. 6.3.5  Boost Capacitor (BOOT)
      6. 6.3.6  Output Feedback (VSENSE)
      7. 6.3.7  Internal Compensation
      8. 6.3.8  Voltage Feed Forward
      9. 6.3.9  Pulse-Width-Modulation (PWM) Control
      10. 6.3.10 Overcurrent Limiting
      11. 6.3.11 Overvoltage Protection (OVP)
      12. 6.3.12 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Minimum Input Voltage
      2. 6.4.2 ENA Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Circuits
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2  Switching Frequency
          3. 7.2.1.2.3  Input Capacitors
          4. 7.2.1.2.4  Output Filter Components
            1. 7.2.1.2.4.1 Inductor Selection
            2. 7.2.1.2.4.2 Capacitor Selection
            3.         44
            4.         45
          5. 7.2.1.2.5  Output Voltage Setpoint
          6. 7.2.1.2.6  Boot Capacitor
          7. 7.2.1.2.7  Catch Diode
          8. 7.2.1.2.8  Output Filter Component Selection
          9. 7.2.1.2.9  External Compensation Network
          10. 7.2.1.2.10 Advanced Information
            1. 7.2.1.2.10.1 Output Voltage Limitations
            2. 7.2.1.2.10.2 Internal Compensation Network
            3. 7.2.1.2.10.3 Thermal Calculations
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Additional Circuits
      3. 7.2.3 Circuit Using Ceramic Output Filter Capacitors
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 PCB Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Thermal Information 

THERMAL METRIC(1) TPS5420-Q1   UNIT
D (SOIC)
8 PINs
RθJA Junction-to-ambient thermal resistance (Custom Board)(2) 75 °C/W
RθJA Junction-to-ambient thermal resistance (JESD 51-7)(3)        106 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54 °C/W
RθJB Junction-to-board thermal resistance 55 °C/W
ψJT Junction-to-top characterization parameter 15 °C/W
ψJB Junction-to-board characterization parameter 56 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) Refer to the TPS5420's EVM User's Guide for board layout and additional information.  For thermal design information please see the Maximum Ambient Temperature section.  
(3) The value of RΘJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. These values do not represent the performance obtained in an actual application. For example, the EVM RΘJA = 75 ℃/W. For design information please see the Maximum Ambient Temperature section.