SLVS974F September   2009  – May 2020 TPS54218

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency versus Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft-Start Pin
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Frequency Shift
      13. 7.3.13 Reverse Overcurrent Protection
      14. 7.3.14 Synchronize Using the RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Small Signal Model for Loop Response
      2. 7.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 7.4.3 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Step One: Select the Switching Frequency
        2. 8.2.2.2  Step Two: Select the Output Inductor
        3. 8.2.2.3  Step Three: Choose the Output Capacitor
        4. 8.2.2.4  Step Four: Select the Input Capacitor
        5. 8.2.2.5  Step Five: Minimum Load DC COMP Voltage
        6. 8.2.2.6  Step Six: Choose the Soft-Start Capacitor
        7. 8.2.2.7  Step Seven: Select the Bootstrap Capacitor
        8. 8.2.2.8  Step Eight: Undervoltage Lockout Threshold
        9. 8.2.2.9  Step Nine: Select Output Voltage and Feedback Resistors
          1. 8.2.2.9.1 Output Voltage Limitations
        10. 8.2.2.10 Step 10: Select Loop Compensation Components
        11. 8.2.2.11 Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.4.3 Small Signal Model for Frequency Compensation

The TPS54218 device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 34. The Type-II circuits are most likely implemented in high bandwidth power supply designs using low-ESR output capacitors. In Type-IIA, one additional high frequency pole is added to attenuate high-frequency noise.

TPS54218 freq_comp_slvs974.gifFigure 34. Types of Frequency Compensation

The design guidelines for TPS54218 device loop compensation are as follows:

  1. Calculate the modulator pole (fP(MOD)) and the esr zero, (fZ1) using Equation 11 and Equation 12. If the output voltage is a high percentage of the capacitor rating, it can be necessary to derate the output capacitor (COUT). Use the capacitor manufacturer information to derate the capacitor value. Use Equation 13 and Equation 14 to estimate a starting point for the crossover frequency, fC. Equation 13 shows the geometric mean of the modulator pole and the ESR zero and Equation 14 is the mean of modulator pole and the switching frequency. Use the lower value of Equation 13 or Equation 14 as the maximum crossover frequency.
    2. Equation 11. TPS54218 q_fpmod_slvs946.gif
    Equation 12. TPS54218 q_fzmod_slvs946.gif
    Equation 13. TPS54218 q_fc_1_slvs94.gif
    Equation 14. TPS54218 q_fc_2_slvs94.gif
  2. Calculate resistor R3. Equation 15 shows the calculation for resistor R3.
    3. Equation 15. TPS54218 q_r3_slvs946.gif

    where

    • gM(ea) is the amplifier gain (225 μA/V)
    • gM(ps) is the power stage gain (13 A/V)
  3. Place a compensation zero at the dominant pole, fP. Equation 16 shows the calculation for capacitor C1.
    4. Equation 16. TPS54218 q_fp_slvs946.gif
    Equation 17. TPS54218 eq10_c1_lvs946.gif
  4. Capacitor C2 is optional. It can be used to cancel the zero from the output capacitor (COUT) ESR.
    5. Equation 18. TPS54218 eq11_c2_lvs975.gif