SLVSDF5D September 2017 – October 2019 TPS50601A-SP
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Supply Voltage (VIN AND PVIN Pins) | ||||||
PVIN operating input voltage | 3 | 7 | V | |||
PVIN internal UVLO threshold | PVIN rising | 2.50 | V | |||
PVIN internal UVLO hysteresis | 450 | mV | ||||
VIN operating input voltage | 3 | 7 | V | |||
VIN internal UVLO threshold | VIN rising | 2.75 | 3 | V | ||
VIN internal UVLO hysteresis | 150 | mV | ||||
VIN shutdown supply current | VEN = 0 V | 1.35 | 2.5 | mA | ||
VIN operating – non switching supply current | VSENSE = VBG | 5 | 10 | mA | ||
Enable and UVLO (EN Pin) | ||||||
Enable threshold | Rising | 1.14 | 1.18 | V | ||
Falling | 1.05 | 1.11 | ||||
Input current | VEN = 1.1 V | 6.1 | μA | |||
Hysteresis current | VEN = 1.3 V | 3 | μA | |||
Voltage Reference | ||||||
Voltage reference | 0 A ≤ Iout ≤ 6 A, –55 to 125°C | 0.792 | 0.804 | 0.816 | V | |
REFCAP voltage | 470 nF | 1.211 | V | |||
Mosfet | ||||||
High-side switch resistance | PVIN = VIN = 3 V, lead length = 4 mm | 50 | mΩ | |||
High-side switch resistance(1) | PVIN = VIN = 5 V, lead length = 4 mm | 45 | mΩ | |||
High-side switch resistance(1) | PVIN = VIN = 7 V, lead length = 4 mm | 43 | mΩ | |||
Low-side switch resistance(1) | PVIN = VIN= 3 V, lead length = 4 mm | 35 | mΩ | |||
Low-side switch resistance(1) | PVIN = VIN = 5 V, lead length = 4 mm | 34 | mΩ | |||
Low-side switch resistance(1) | PVIN = VIN = 7 V, lead length = 4 mm | 33 | mΩ | |||
Error Amplifier | ||||||
Error amplifier transconductance (gm)(2) | –2 μA < ICOMP < 2 μA, V(COMP) = 1 V | 1000 | 1400 | 2000 | μS | |
Error amplifier dc gain(2) | VSENSE = 0.804 V | 10000 | V/V | |||
Error amplifier source/sink(2) | V(COMP) = 1 V, 100-mV input overdrive | –250 | ±115 | 250 | μA | |
Error amplifier output resistance | 7 | MΩ | ||||
Start switching threshold(2) | 0.25 | V | ||||
COMP to Iswitch gm(2) | 22 | S | ||||
Current Limit | ||||||
High-side switch current limit threshold (3) | VIN = 7 V | 11 | A | |||
Low-side switch sourcing current limit(3) | VIN = 7 V | 10 | A | |||
Low-side switch sinking current limit | VIN = 7 V | 3 | A | |||
Thermal Shutdown | ||||||
Thermal shutdown | 170 | °C | ||||
Thermal shutdown hysteresis | 30 | °C | ||||
Internal Switching Frequency | ||||||
Internally set frequency | RT = Open | 395 | 500 | 585 | kHz | |
Externally set frequency | RT = 100 kΩ (1%) | 395 | 500 | 585 | kHz | |
RT = 487 kΩ (1%) | 85 | 100 | 120 | |||
RT = 47 kΩ (1%) | 900 | 1000 | 1100 | |||
External Synchronization | ||||||
SYNC out low-to-high rise time (10%/90%) | CLOAD = 25 pF | 70 | 111 | ns | ||
SYNC out high-to-low fall time (90%/10%) | CLOAD = 25 pF | 6 | 15.5 | ns | ||
Falling edge delay time(5) | 180 | ° | ||||
SYNC out high level threshold | IOH = 50 µA | VIN - 0.3 | V | |||
SYNC out low level threshold | IOL = 50 µA | 600 | mV | |||
SYNC in low level threshold | PVIN = VIN = 3 V | 900 | mV | |||
SYNC in high level threshold | PVIN = VIN = 3 V | 2.45 | V | |||
SYNC in low level threshold | PVIN = VIN = 7 V | 900 | mV | |||
SYNC in high level threshold | PVIN = VIN = 7 V | 4.25 | V | |||
SYNC in frequency range(4) | 100 | 1000 | kHz | |||
PH (PH Pin) | ||||||
Minimum on time | Measured at 10% to 90% of VIN,
25°C, IPH = 2 A |
190 | 235 | ns | ||
Slow Start and Tracking (SS/TR Pin) | ||||||
SS charge current | 1.5 | 2.5 | 3 | μA | ||
SS/TR to VSENSE matching | V(SS/TR) = 0.4 V | 30 | 90 | mV | ||
Power Good (PWRGD Pin) | ||||||
VSENSE threshold | VSENSE falling (fault) | 91 | % VREF | |||
VSENSE rising (good) | 94 | |||||
VSENSE rising (fault) | 109 | |||||
VSENSE falling (good) | 106 | |||||
Output high leakage | VSENSE = VREF, V(PWRGD) = 5 V | 30 | 181 | nA | ||
Output low | I(PWRGD) = 2 mA | 0.3 | V | |||
Minimum VIN for valid output | V(PWRGD) < 0.5 V at 100 μA | 0.6 | 1 | V | ||
Minimum SS/TR voltage for PWRGD | 1.55 | V |