SLVSDR3C may   2018  – may 2023 ADC12DL3200

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
        5. 7.3.2.5 Internal Dither
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 LVDS Digital Interface
        1. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 7.3.5.1.1 Dedicated Strobe Pins
          2. 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 7.3.5.1.3 LSB Replacement With a Strobe
          4. 7.3.5.1.4 Strobe Over All Data Pairs
      6. 7.3.6 Alarm Monitoring
        1. 7.3.6.1 Clock Upset Detection
      7. 7.3.7 Temperature Monitoring Diode
      8. 7.3.8 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 7.4.2 Internal Dither Modes
      3. 7.4.3 Single-Channel Mode (DES Mode)
      4. 7.4.4 LVDS Output Driver Modes
      5. 7.4.5 LVDS Output Modes
        1. 7.4.5.1 Staggered Output Mode
        2. 7.4.5.2 Aligned Output Mode
        3. 7.4.5.3 Reducing the Number of Strobes
        4. 7.4.5.4 Reducing the Number of Data Clocks
        5. 7.4.5.5 Scrambling
        6. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 7.4.5.6.1 Active Pattern
          2. 7.4.5.6.2 Synchronization Pattern
          3. 7.4.5.6.3 User-Defined Test Pattern
      6. 7.4.6 Power-Down Modes
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 78
        6. 7.5.1.6 Streaming Mode
        7. 7.5.1.7 80
    6. 7.6 Register Maps
      1. 7.6.1 SPI_REGISTER_MAP Registers
  9.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 The ADC12DL3200
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9Mechanical, Packaging, and Orderable Information

SPI_REGISTER_MAP Registers

Table 7-18 lists the memory-mapped registers for the SPI_REGISTER_MAP. All register offset addresses not listed in Table 7-18 are considered reserved locations and the register contents are not to be modified.

Table 7-18 SPI_REGISTER_MAP Registers
AddressAcronymRegister NameSection
0x000CONFIG_AConfiguration A (Default: 0x30)Go
0x002DEVICE_CONFIGDevice Configuration (Default: 0x00)Go
0x003CHIP_TYPEChip Type (Default: 0x03)Go
0x004-0x005CHIP_IDChip IdentificationGo
0x00C-0x00DVENDOR_IDVendor Identification (Default: 0x0451)Go
0x010USR0User SPI Configuration (Default: 0x00)Go
0x029CLK_CTRL0Clock Control 0 (Default: 0x00)Go
0x02ACLK_CTRL1Clock Control 1 (Default: 0x00)Go
0x02C-0x02ESYSREF_POSSYSREF Capture Position (Read-only status)Go
0x030-0x031FS_RANGE_AFull-Scale Voltage for INA± (Default: 0xA000)Go
0x032-0x033FS_RANGE_BFull-Scale Voltage for INB± (Default: 0xA000)Go
0x038BG_BYPASSBand-Gap Bypass (Default: 0x00)Go
0x03BSYNC_CTRLSYNC_SE/TIMESTAMP Control (Default: 0x00)Go
0x048LVDS_SWINGLVDS Swing Mode (Default: 0x00)Go
0x060INPUT_MUXInput Mux Control (Default: 0x01)Go
0x061CAL_ENCalibration Enable (Default: 0x01)Go
0x062CAL_CFG0Calibration Configuration 0 (Default: 0x01)Go
0x06ACAL_STATUSCalibration Status (Default: undefined; read-only)Go
0x06BCAL_PIN_CFGCalibration Pin Configuration (Default: 0x00)Go
0x06CCAL_SOFT_TRIGCalibration Software Trigger (Default: 0x01)Go
0x06ECAL_LPLow-Power Background Calibration (Default: 0x88)Go
0x070CAL_DATA_ENCalibration Data Enable (Default: 0x00)Go
0x071CAL_DATACalibration Data (Default: undefined)Go
0x07AGAIN_TRIM_AGain DAC Trim A (Default from fuse ROM)Go
0x07BGAIN_TRIM_BGain DAC Trim B (Default from fuse ROM)Go
0x07CBG_TRIMBand-Gap Trim (Default from fuse ROM)Go
0x07ERTRIM_AResistor TRIM for INA± (Default from fuse ROM)Go
0x07FRTRIM_BResistor TRIM for INB± (Default from fuse ROM)Go
0x09DADC_DITHADC Dither register (Default: 0x01)Go
0x102B0_TIME_0Time Adjustment for Bank 0 (0° clock) (Default from fuse ROM)Go
0x103B0_TIME_90Time Adjustment for Bank 0 (–90° clock) (Default from fuse ROM)Go
0x112B1_TIME_0Time Adjustment for Bank 1 (0° clock) (Default from fuse ROM)Go
0x113B1_TIME_90Time Adjustment for Bank 1 (–90° clock) (Default from fuse ROM)Go
0x142B4_TIME_0Time Adjustment for Bank 4 (0° clock) (Default from fuse ROM)Go
0x152B5_TIME_0Time Adjustment for Bank 5 (0° clock) (Default from fuse ROM)Go
0x160LSB_CTRLLSB Control Bit Output (Default: 0x00)Go
0x161LSB_SELLSB Control Bit Position (Default: 0x00)Go
0x180-0x181UPAT0User-Defined Pattern (Sample 0; default: 0x0000)Go
0x182-0x183UPAT1User-Defined Pattern (Sample 1; default: 0x0FFF; same format as UPAT0)Go
0x184-0x185UPAT2User-Defined Pattern (Sample 2; default: 0x0000; same format as UPAT0)Go
0x186-0x187UPAT3User-Defined Pattern (Sample 3; default: 0x0FFF; same format as UPAT0)Go
0x188-0x189UPAT4User-Defined Pattern (Sample 4; default: 0x0000; same format as UPAT0)Go
0x18A-0x18BUPAT5User-Defined Pattern (Sample 5; default: 0x0FFF; same format as UPAT0)Go
0x18C-0x18DUPAT6User-Defined Pattern (Sample 6; default: 0x0000; same format as UPAT0)Go
0x18E-0x18FUPAT7User-Defined Pattern (Sample 7; default: 0x0FFF; same format as UPAT0)Go
0x190UPAT_CTRLUser-Defined Pattern Control (Default: 0x1E)Go
0x200LVDS_ENLVDS Subsystem Enable (Default: 0x01)Go
0x201LMODELVDS Mode (Default: 0x01)Go
0x202LFRAMELVDS Frame Length (Default: 0x80; 128 decimal)Go
0x203LSYNC_NLVDS Manual Sync Request (Default: 0x01)Go
0x204LCTRLLVDS Control (Default: 0x02)Go
0x205PAT_SELLVDS Pattern Control (Default: 0x02)Go
0x206LCS_ENLVDS Clock and Strobe Enables (Default: 0xFF)Go
0x208LVDS_STATUSSystem Status RegisterGo
0x209PD_CHADC Channel Power-Down (Default: 0x00)Go
0x211OVR_T0Overrange Threshold 0 (Default: 0xF2)Go
0x212OVR_T1Overrange Threshold 1 (Default: 0xAB)Go
0x213OVR_CFGOverrange Enable/Hold Off (Default: 0x07)Go
0x297SPIN_IDChip Spin Identifier (Default from fuse ROM; read-only)Go
0x2B0SRC_ENSYSREF Calibration Enable (Default: 0x00)Go
0x2B1SRC_CFGSYSREF Calibration Configuration (Default: 0x05)Go
0x2B2-0x2B4SRC_STATUSSYSREF Calibration Status (Default: undefined; read-only)Go
0x2B5-0x2B7TADCLK± Timing Adjust (Default: 0x00)Go
0x2B8TAD_RAMPCLK± Timing Adjust Ramp Control (Default: 0x00)Go
0x2C0ALARMAlarm Interrupt (Read-only)Go
0x2C1ALM_STATUSAlarm Status (Default: 0x05; write to clear)Go
0x2C2ALM_MASKAlarm Mask Register (Default: 0x05)Go
0x310TADJ_ATiming Adjust for A-ADC, Dual Mode (Default from fuse ROM)Go
0x313TADJ_BTiming Adjust for B-ADC, Dual Mode (Default from fuse ROM)Go
0x314TADJ_A_FG90_VINATiming Adjust for A-ADC, DES, Foreground Calibration, INA± (Default from fuse ROM)Go
0x315TADJ_B_FG0_VINATiming Adjust for B-ADC, DES, Foreground Calibration, INA± (Default from fuse ROM)Go
0x31ATADJ_A_FG90_VINBTiming Adjust for A-ADC, DES, Foreground Calibration, INB± (Default from fuse ROM)Go
0x31BTADJ_B_FG0_VINBTiming Adjust for B-ADC, DES, Foreground Calibration, INB± (Default from fuse ROM)Go
0x344-0x345OADJ_A_FG0_VINAOffset Adjustment for A-ADC, Foreground Calibration, 0° Clock, INA± (Default from fuse ROM)Go
0x346-0x347OADJ_A_FG0_VINBOffset Adjustment for A-ADC, Foreground Calibration, 0° Clock, INB± (Default from fuse ROM)Go
0x348-0x349OADJ_A_FG90_VINAOffset Adjustment for A-ADC, Foreground Calibration, 90° Clock, INA± (Default from fuse ROM)Go
0x34A-0x34BOADJ_A_FG90_VINBOffset Adjustment for A-ADC, Foreground Calibration, 90° Clock, INB± (Default from fuse ROM)Go
0x34C-0x34DOADJ_B_FG0_VINAOffset Adjustment for B-ADC, Foreground Calibration, INA± (Default from fuse ROM)Go
0x34E-0x34FOADJ_B_FG0_VINBOffset Adjustment for B-ADC, Foreground Calibration, INB± (Default from fuse ROM)Go
0x360GAIN_B0Fine Gain Adjust for Bank 0 (Default from fuse ROM)Go
0x361GAIN_B1Fine Gain Adjust for Bank 1 (Default from fuse ROM)Go
0x364GAIN_B4Fine Gain Adjust for Bank 4 (Default from fuse ROM)Go
0x365GAIN_B5Fine Gain Adjust for Bank 5 (Default from fuse ROM)Go

Complex bit access types are encoded to fit into small table cells. Table 7-19 shows the codes that are used for access types in this section.

Table 7-19 SPI_REGISTER_MAP Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1.1 CONFIG_A Register (Address = 0x000) [reset = 0x30]

CONFIG_A is shown in Figure 7-7 and described in Table 7-20.

Return to Summary Table.

Configuration A register (default: 0x30). This register controls device reset and SPI interface parameters.

Figure 7-7 CONFIG_A Register
76543210
SOFT_RESETRESERVEDASCENDSDO_ACTIVERESERVED
R/W-0x0R/W-0x0R/W-0x1R-0x1R/W-0x0
Table 7-20 CONFIG_A Register Field Descriptions
BitFieldTypeResetDescription
7SOFT_RESETR/W0x0

Setting this bit causes a full reset of the device and all SPI registers (including CONFIG_A). This bit is self-clearing. After writing this bit, the device may take up to 750 ns to reset. During this time, do not perform any SPI transactions.

6RESERVEDR/W0x0

Reserved

5ASCENDR/W0x1

0 : Address is decremented during streaming reads or writes
1 : Address is incremented during streaming reads or writes (default)

4SDO_ACTIVER0x1

Always returns 1. Always use SDO for SPI reads.
No SDIO mode is supported.

3-0RESERVEDR/W0x0

Reserved

7.6.1.2 DEVICE_CONFIG Register (Address = 0x002) [reset = 0x00]

DEVICE_CONFIG is shown in Figure 7-8 and described in Table 7-21.

Return to Summary Table.

Device Configuration register (default: 0x00). This device controls the power-down of the device.

Figure 7-8 DEVICE_CONFIG Register
76543210
RESERVEDMODE
R/W-0x0R/W-0x0
Table 7-21 DEVICE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0x0

Reserved

1-0MODER/W0x0

0 : Normal operation (default)
1 : Reserved
2 : Reserved
3 : Power-down

7.6.1.3 CHIP_TYPE Register (Address = 0x003) [reset = 0x03]

CHIP_TYPE is shown in Figure 7-9 and described in Table 7-22.

Return to Summary Table.

Chip Type register (default: 0x03). This register returns the chip type.

Figure 7-9 CHIP_TYPE Register
76543210
RESERVEDCHIP_TYPE
R/W-0x0R-0x3
Table 7-22 CHIP_TYPE Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0x0

Reserved

3-0CHIP_TYPER0x3

Always returns 0x3, indicating that the device is a high-speed ADC.

7.6.1.4 CHIP_ID Register (Address = 0x004) [reset = 0x0022]

CHIP_ID is shown in Figure 7-10 and described in Table 7-23.

Return to Summary Table.

Chip Identification register (default: 0x0022). This register returns the chip identification number.

Figure 7-10 CHIP_ID Register
1514131211109876543210
CHIP_ID
R-0x0022
Table 7-23 CHIP_ID Register Field Descriptions
BitFieldTypeResetDescription
15-0CHIP_IDR0x0022

Returns 0x0022, indicating the device is an ADC12DL3200.

7.6.1.5 VENDOR_ID Register (Address = 0xC) [reset = 0x0451]

VENDOR_ID is shown in Figure 7-11 and described in Table 7-24.

Return to Summary Table.

Vendor Identification register (default = 0x0451). This register returns the vendor identification number.

Figure 7-11 VENDOR_ID Register
1514131211109876543210
VENDOR_ID
R-0x0451
Table 7-24 VENDOR_ID Register Field Descriptions
BitFieldTypeResetDescription
15-0VENDOR_IDR0x0451

Always returns 0x0451 (vendor ID for Texas Instruments).

7.6.1.6 USR0 Register (Address = 0x010) [reset = 0x00]

USR0 is shown in Figure 7-12 and described in Table 7-25.

Return to Summary Table.

User SPI Configuration register (default: 0x00). This register enables holding of the current address during streaming SPI transactions.

Figure 7-12 USR0 Register
76543210
RESERVEDADDR_HOLD
R/W-0x0R/W-0x0
Table 7-25 USR0 Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0ADDR_HOLDR/W0x0

0 : Use the ASCEND register to select address ascend or descend mode (default)
1 : Address stays constant throughout streaming operation; useful for reading and writing calibration vector information at the CAL_DATA register

7.6.1.7 CLK_CTRL0 Register (Address = 0x029) [reset = 0x00]

CLK_CTRL0 is shown in Figure 7-13 and described in Table 7-26.

Return to Summary Table.

Clock Control 0 register (default: 0x00). This register is used to control the SYSREF receiver (SYSREF±), processing of the SYSREF signal and the SYSREF windowing zoom and delay settings.

Figure 7-13 CLK_CTRL0 Register
76543210
RESERVEDSYSREF_PROC_ENSYSREF_RECV_ENSYSREF_ZOOMSYSREF_SEL
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-26 CLK_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0

Reserved

6SYSREF_PROC_ENR/W0x0

This bit enables the SYSREF processor, which allows the device to process SYSREF events (default: disabled). SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN.

5SYSREF_RECV_ENR/W0x0

Set this bit to enable the SYSREF receiver circuit (default: disabled).

4SYSREF_ZOOMR/W0x0

Set this bit to zoom in the SYSREF windowing status and delays (impacts SYSERF_POS and SYSREF_SEL). When set, the delays used in the SYSREF windowing feature (reported in the SYSREF_POS register) become smaller. Use SYSREF_ZOOM for high clock rates, specifically when multiple SYSREF valid windows are encountered in the SYSREF_POS register; see the Section 7.3.4.3.1 section.

3-0SYSREF_SELR/W0x0

Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS; see the Section 7.3.4.3.1 section. These bits must be set to 0 to use SYSREF calibration; see the Section 7.3.4.3.2 section.

7.6.1.8 CLK_CTRL1 Register (Address = 0x02A) [reset = 0x00]

CLK_CTRL1 is shown in Figure 7-14 and described in Table 7-27.

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Clock Control 1 register (default: 0x00). This register allows SYSREF to be used as the timestamp input, allows inversion of the SYSREF signal, and enables the DC-coupled receiver mode for the CLK± and SYSREF± inputs.

Figure 7-14 CLK_CTRL1 Register
76543210
RESERVEDSYSREF_TIME_STAMP_ENDEVCLK_LVPECL_ENSYSREF_LVPECL_ENSYSREF_INVERTED
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-27 CLK_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0x0

Reserved

3SYSREF_TIME_STAMP_ENR/W0x0

The SYSREF signal is output on the LSB of the LVDS output samples when SYSREF_TIMESTAMP_EN and TIME_STAMP_EN are both set. This bit allows SYSREF± to be used as the timestamp input.

2DEVCLK_LVPECL_ENR/W0x0

Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin Functions table.

1SYSREF_LVPECL_ENR/W0x0

Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the Pin Functions table.

0SYSREF_INVERTEDR/W0x0

This bit inverts the SYSREF signal used for alignment.

7.6.1.9 SYSREF_POS Register (Address = 0x02C-0x02E) [reset = Undefined]

SYSREF_POS is shown in Figure 7-15 and described in Table 7-28.

Return to Summary Table.

SYSREF Capture Position register (read-only status). This register is used by the SYSREF windowing feature to report back the valid SYSREF capture windows; see the Section 7.3.4.3.1 section.

Figure 7-15 SYSREF_POS Register
2322212019181716
SYSREF_POS[23:16]
R-Undefined
15141312111098
SYSREF_POS[15:8]
R-Undefined
76543210
SYSREF_POS[7:0]
R-Undefined
Table 7-28 SYSREF_POS Register Field Descriptions
BitFieldTypeResetDescription
23-0SYSREF_POSR/WUndefined

Returns a 24-bit status value that indicates the position of the SYSREF edge with respect to CLK±. Use this field to program SYSREF_SEL.

7.6.1.10 INA Full-Scale Range Adjust Register (Address = 0x030-0x031) [reset = 0xA000]

FS_RANGE_A is shown in Figure 7-16 and described in Table 7-29.

Return to Summary Table.

INA± Full-Scale Range Adjust register (default: 0xA000). This register is used to change the full-scale input voltage of the INA± input. Calibration must be performed after changing this register; see the Section 7.3.1.2 section.

Figure 7-16 FS_RANGE_A Register
1514131211109876543210
FS_RANGE_A
R/W-0xA000
Table 7-29 FS_RANGE_A Register Field Descriptions
BitFieldTypeResetDescription
15-0FS_RANGE_AR/W0xA000

These bits enable adjustment of the analog full-scale range for INA±.

0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting

7.6.1.11 INB Full-Scale Range Adjust Register (Address = 0x032-0x033) [reset = 0xA000]

FS_RANGE_B is shown in Figure 7-17 and described in Table 7-30.

Return to Summary Table.

INB± Full-Scale Range Adjust register (default: 0xA000). This register is used to change the full-scale input voltage of the INB± input. Calibration must be performed after changing this register; see the Section 7.3.1.2 section.

Figure 7-17 FS_RANGE_B Register
1514131211109876543210
FS_RANGE_B
R/W-0xA000
Table 7-30 FS_RANGE_B Register Field Descriptions
BitFieldTypeResetDescription
15-0FS_RANGE_BR/W0xA000

These bits enable adjustment of the analog full-scale range for INB±.

0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting

7.6.1.12 BG_BYPASS Register (Address = 0x038) [reset = 0x00]

BG_BYPASS is shown in Figure 7-18 and described in Table 7-31.

Return to Summary Table.

Band-Gap Bypass register (default: 0x00). This register can be used to bypass the internal reference and use the VA11 supply voltage instead.

Figure 7-18 BG_BYPASS Register
76543210
RESERVEDBG_BYPASS
R/W-0x0R/W-0x0
Table 7-31 BG_BYPASS Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0BG_BYPASSR/W0x0

When set, VA11 is used as the voltage reference instead of the band-gap voltage.

7.6.1.13 TMSTP_CTRL Register (Address = 0x03B) [reset = 0x00]

TMSTP_CTRL is shown in Figure 7-19 and described in Table 7-32.

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TMSTP± and Differential SYNC Control register (default: 0x00). This register enables or disables the TMSTP± input and determines the termination scheme for this input.

Figure 7-19 TMSTP_CTRL Register
76543210
RESERVEDTMSTP_LVPECL_ENTMSTP_RECV_EN
R/W-0x0R/W-0x0R/W-0x0
Table 7-32 SYNC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0x0

Reserved

1TMSTP_LVPECL_ENR/W0x0

When set, this bit activates the DC-coupled, low-voltage PECL mode for the differential TMSTP± receiver; see the Pin Functions table.

0TMSTP_RECV_ENR/W0x0

This bit enables the differential TMSTP± receiver.

7.6.1.14 LVDS_SWING Register (Address = 0x048) [reset = 0x00]

LVDS_SWING is shown in Figure 7-20 and described in Table 7-33.

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LVDS Swing Mode register (default: 0x00). This register determines the operating mode of the LVDS output drivers.

Figure 7-20 LVDS_SWING Register
76543210
RESERVEDLVDS_SWING
R/W-0x0R/W-0x0
Table 7-33 LVDS_SWING Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0x0

Reserved

1-0LVDS_SWINGR/W0x0

These bits set the swing mode of the LVDS output buffers:
0 : High-swing mode (HSM) (default)
1 : Low-swing mode (LSM)
2 : Reserved (do not use)
3 : Low-swing mode for use with receivers that have a high-Z load termination (HZM). Only use with short transmission lines to avoid reflections caused by a high-Z receiver.

7.6.1.15 INPUT_MUX Register (Address = 0x060) [reset = 0x01]

INPUT_MUX is shown in Figure 7-21 and described in Table 7-34.

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Input Mux Control register (default: 0x01). This register controls the input used in single-channel mode and the swapping of inputs in dual-channel mode; see the Section 7.3.1 section.

Figure 7-21 INPUT_MUX Register
76543210
RESERVEDDUAL_INPUTRESERVEDSINGLE_INPUT
R/W-0x0R/W-0x0R/W-0x0R/W-0x1
Table 7-34 INPUT_MUX Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0x0

Reserved

4DUAL_INPUTR/W0x0

This bit selects the input for dual-channel mode (non-DES mode). Only applies if DES_EN = 0.
0 : Channel A samples INA±, channel B samples INB± (no swap) (default)
1 : Channel A samples INB±, channel B samples INA± (swap)

3-2RESERVEDR/W0x0

Reserved

1-0SINGLE_INPUTR/W0x1

These bits define which chip input is sampled in single-channel mode (DES mode). Only applies if DES_EN = 1.
0 : Reserved
1 : INA± is sampled (DESA mode)
2 : INB± is sampled (DESB mode)
3 : Reserved

7.6.1.16 CAL_EN Register (Address = 0x61) [reset = 0x01]

CAL_EN is shown in Figure 7-22 and described in Table 7-35.

Return to Summary Table.

Calibration Enable register (default: 0x01). This register is used to enable or disable ADC core calibration.

Figure 7-22 CAL_EN Register
76543210
RESERVEDCAL_EN
R/W-0x0R/W-0x1
Table 7-35 CAL_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0CAL_ENR/W0x1

This bit enables calibration. Set this bit high to run calibration. Set this bit low to hold calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the encoders and LVDS interface.

Note 1: Many calibration SPI registers are not synchronized to the internal clock that runs the calibration logic. Changing these registers may corrupt the calibration state machine. Always clear CAL_EN before making any changes to these registers. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings.

Note 2: Always set CAL_EN before setting LVDS_EN.

Note 3: Always clear LVDS_EN before clearing CAL_EN.

7.6.1.17 CAL_CFG0 Register (Address = 0x062) [reset = 0x01]

CAL_CFG0 is shown in Figure 7-23 and described in Table 7-36.

Return to Summary Table.

Calibration Configuration 0 register (default: 0x01). This register controls offset calibration and sets whether foreground or background calibration is used. Only change this register when CAL_EN is 0.

Figure 7-23 CAL_CFG0 Register
76543210
RESERVEDCAL_BGOSCAL_OSCAL_BGCAL_FG
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x1
Table 7-36 CAL_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0x0

Reserved

3CAL_BGOSR/W0x0

0 : Disable background offset calibration (default)
1 : Enable background offset calibration (requires CAL_BG to be set).

2CAL_OSR/W0x0

0 : Disable foreground offset calibration (default)
1 : Enable foreground offset calibration (requires CAL_FG to be set)

1CAL_BGR/W0x0

0 : Disable background calibration (default)
1 : Enable background calibration

0CAL_FGR/W0x1

0 : Reset calibration values, skip foreground calibration.
1 : Reset calibration values, then run foreground calibration (default).

7.6.1.18 CAL_AVG Register (Address = 0x68) [reset = 0x61]

CAL_AVG is shown in Figure 7-24 and described in Table 7-37.

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Calibration Averaging register (default: 0x61). This address determines the amount of averaging used for offset calibration.

Figure 7-24 CAL_AVG Register
76543210
RESERVEDOS_AVGRESERVED
R/W-0x0R/W-0x6R-0x1
Table 7-37 CAL_AVG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0

Reserved

6-4OS_AVGR/W0x6

Select the amount of averaging used for each measurement of the offset correction search. A larger number corresponds to more averaging.

3-0RESERVEDR0x1Always write 0x1.

7.6.1.19 CAL_STATUS Register (Address = 0x06A) [reset = Undefined]

CAL_STATUS is shown in Figure 7-25 and described in Table 7-38.

Return to Summary Table.

Calibration Status register (default: Undefined) (read-only). This register is used to read out the calibration status information.

Figure 7-25 CAL_STATUS Register
76543210
RESERVEDCAL_STATCAL_STOPPEDFG_DONE
R-UndefinedR-UndefinedR-UndefinedR-Undefined
Table 7-38 CAL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDRUndefined

Reserved

4-2CAL_STATRUndefinedCalibration status code
1CAL_STOPPEDRUndefinedThis bit returns a 1 when background calibration is successfully stopped at the requested phase. This bit returns a 0 when calibration starts operating again. If background calibration is disabled, this bit is set when foreground calibration is completed or skipped.
0FG_DONERUndefined

This bit is high to indicate that foreground calibration has completed (or was skipped).

7.6.1.20 CAL_PIN_CFG Register (Address = 0x06B) [reset = 0x00]

CAL_PIN_CFG is shown in Figure 7-26 and described in Table 7-39.

Return to Summary Table.

Calibration Pin Configuration register (default: 0x00). This register sets the function of the CALSTAT pin and selects whether hardware or software CALTRIG is used.

Figure 7-26 CAL_PIN_CFG Register
76543210
RESERVEDCAL_STATUS_SELCAL_TRIG_EN
R/W-0x0R/W-0x0R/W-0x0
Table 7-39 CAL_PIN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0x0

Reserved

2-1CAL_STATUS_SELR/W0x0

0 : CALSTAT output pin matches FG_DONE
1 : CALSTAT output pin matches CAL_STOPPED
2 : CALSTAT output pin matches ALARM
3 : CALSTAT output is always low

0CAL_TRIG_ENR/W0x0

This bit selects the hardware or software trigger source.
0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The CALTRIG input is disabled (ignored).
1 : Use the CALTRIG input for the calibration trigger. The CAL_SOFT_TRIG register is ignored.

7.6.1.21 CAL_SOFT_TRIG Register (Address = 0x06C) [reset = 0x01]

CAL_SOFT_TRIG is shown in Figure 7-27 and described in Table 7-40.

Return to Summary Table.

Calibration Software Trigger register (default: 0x01). This register is used as the software CALTRIG.

Figure 7-27 CAL_SOFT_TRIG Register
76543210
RESERVEDCAL_SOFT_TRIG
R/W-0x0R/W-0x1
Table 7-40 CAL_SOFT_TRIG Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0CAL_SOFT_TRIGR/W0x1

CAL_SOFT_TRIG is a software bit to provide the functionality of the CALTRIG input when there are no hardware resources to drive CALTRIG. Program CAL_TRIG_EN = 0 to use CAL_SOFT_TRIG for the calibration trigger.

Note: If no calibration trigger is needed, leave CAL_TRIG_EN = 0 and CAL_SOFT_TRIG = 1 (trigger set high).

7.6.1.22 Low-Power Background Calibration Register (Address = 0x6E) [reset = 0x88]

CAL_LP is shown in Figure 7-28 and described in Table 7-41.

Return to Summary Table.

Low-Power Background Calibration register (default: 0x88). This register enables low-power background calibration and sets the parameters for low-power background calibration.

Figure 7-28 CAL_LP Register
76543210
LP_SLEEP_DLYLP_WAKE_DLYRESERVEDLP_TRIGLP_EN
R/W-0x4R/W-0x1R/W-0x0R/W-0x0R/W-0x0
Table 7-41 CAL_LP Register Field Descriptions
BitFieldTypeResetDescription
7-5LP_SLEEP_DLYR/W0x4

These bits adjust how long an ADC sleeps before waking for calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values below 4 are not recommended because of limited overall power reduction benefits.

0: Sleep delay = (23 + 1) × 256 × tCLK
1: Sleep delay = (215 + 1) × 256 × tCLK
2: Sleep delay = (218 + 1) × 256 × tCLK
3: Sleep delay = (221 + 1) × 256 × tCLK
4: Sleep delay = (224 + 1) × 256 × tCLK (default, approximately 1.338 seconds with a 3.2-GHz clock)
5: Sleep delay = (227 + 1) × 256 × tCLK
6: Sleep delay = (230 + 1) × 256 × tCLK
7: Sleep delay = (233 + 1) × 256 × tCLK

4-3LP_WAKE_DLYR/W0x1These bits adjust how much time is provided for settling before calibrating an ADC after the ADC wakes up (only applies when LP_EN = 1). Values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins.

0: Wake delay = (23 + 1) × 256 × tCLK
1: Wake delay = (218 + 1) × 256 × tCLK (default, approximately 21 ms with a 3.2-GHz clock)
2: Wake delay = (221 + 1) × 256 × tCLK
3: Wake delay = (224 + 1) × 256 × tCLK
2RESERVEDMust write 0x0.
1LP_TRIGR/W0x00: ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode).
1: ADCs sleep until woken by a trigger. An ADC is woken when the calibration trigger (the CAL_SOFT_TRIG bit or CAL_TRIG input) is low.
0LP_ENR/W0x00: Disable low-power background calibration (default)
1: Enable low-power background calibration (only applies when CAL_BG = 1).

7.6.1.23 CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]

CAL_DATA_EN is shown in Figure 7-29 and described in Table 7-42.

Return to Summary Table.

Calibration Data Enable register (default: 0x00). This register enables reading calibration data.

Figure 7-29 CAL_DATA_EN Register
76543210
RESERVEDCAL_DATA_EN
R/W-0x0R/W-0x0
Table 7-42 CAL_DATA_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0CAL_DATA_ENR/W0x0Set this bit to enable the CAL_DATA register to enable reading and writing of calibration data; see the CAL_DATA register for more information.

7.6.1.24 CAL_DATA Register (Address = 0x71) [reset = Undefined]

CAL_DATA is shown in Figure 7-30 and described in Table 7-43.

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Calibration Data register (default: Undefined). This register is used to read out the calibration data.

Figure 7-30 CAL_DATA Register
76543210
CAL_DATA
R/W-0x0
Table 7-43 CAL_DATA Register Field Descriptions
BitFieldTypeResetDescription
7-0CAL_DATAR/W0x0

After setting CAL_DATA_EN, repeated reads of this register return all calibration values for the ADCs. Repeated writes of this register input all calibration values for the ADCs. To read the calibration data, read the register 673 times. To write the vector, write the register 673 times with previously stored calibration data. To speed up the read or write operation, set ADDR_HOLD = 1 and use streaming read or write process. IMPORTANT: Accessing the CAL_DATA register when CAL_STOPPED = 0 corrupts the calibration. Also, stopping the process before reading or writing 673 times leaves the calibration data in an invalid state.

7.6.1.25 GAIN_TRIM_A Register (Address = 0x07A) [reset = Undefined]

GAIN_TRIM_A is shown in Figure 7-31 and described in Table 7-44.

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Gain DAC Trim A register (default from fuse ROM). This register is used for trimming the INA± gain.

Figure 7-31 GAIN_TRIM_A Register
76543210
GAIN_TRIM_A
R/W-Undefined
Table 7-44 GAIN_TRIM_A Register Field Descriptions
BitFieldTypeResetDescription
7-0GAIN_TRIM_AR/WUndefined

This register enables gain trim of channel A. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_A to adjust the analog full-scale voltage (Vfs) of INA±.

7.6.1.26 GAIN_TRIM_B Register (Address = 0x07B) [reset = Undefined]

GAIN_TRIM_B is shown in Figure 7-32 and described in Table 7-45.

Return to Summary Table.

Gain DAC Trim B register (default from fuse ROM). This register is used for trimming the INB± gain.

Figure 7-32 GAIN_TRIM_B Register
76543210
GAIN_TRIM_B
R/W-Undefined
Table 7-45 GAIN_TRIM_B Register Field Descriptions
BitFieldTypeResetDescription
7-0GAIN_TRIM_BR/WUndefinedThis register enables gain trim of channel B. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_B to adjust the analog full-scale voltage (Vfs) of INB±.

7.6.1.27 BG_TRIM Register (Address = 0x07C) [reset = Undefined]

BG_TRIM is shown in Figure 7-33 and described in Table 7-46.

Return to Summary Table.

Band-Gap Trim register (default from fuse ROM). Use this register to trim the internal band-gap reference. The voltage can be measured on the BG pin.

Figure 7-33 BG_TRIM Register
76543210
RESERVEDBG_TRIM
R/W-0x0R/W-Undefined
Table 7-46 BG_TRIM Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0x0

Reserved

3-0BG_TRIMR/WUndefined

This register enables trimming of the internal band-gap reference. After reset, the factory trimmed value can be read and adjusted as required.

7.6.1.28 RTRIM_A Register (Address = 0x07E) [reset = Undefined]

RTRIM_A is shown in Figure 7-34 and described in Table 7-47.

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Resistor TRIM for INA± register (default from fuse ROM). This register can be used to trim the input termination resistance of INA±.

Figure 7-34 RTRIM_A Register
76543210
RTRIM_A
R/W-Undefined
Table 7-47 RTRIM_A Register Field Descriptions
BitFieldTypeResetDescription
7-0RTRIM_AR/WUndefined

This register controls the INA± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

7.6.1.29 RTRIM_B Register (Address = 0x7F) [reset = Undefined]

RTRIM_B is shown in Figure 7-35 and described in Table 7-48.

Return to Summary Table.

Resistor TRIM for INB± (default from fuse ROM). This register can be used to trim the input termination resistance of INB±.

Figure 7-35 RTRIM_B Register
76543210
RTRIM_B
R/W-Undefined
Table 7-48 RTRIM_B Register Field Descriptions
BitFieldTypeResetDescription
7-0RTRIM_BR/WUndefinedThis register controls the INB± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

7.6.1.30 ADC_DITH Register (Address = 0x9D) [reset = 0x01]

ADC_DITH is shown in Figure 7-36 and described in Table 7-49.

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ADC Dither register (default: 0x01). This register can be used enable or disable ADC dither and to adjust the amount of dither used.

Figure 7-36 ADC_DITH Register
76543210
RESERVEDADC_DITH_ERRADC_DITH_AMPADC_DITH_EN
R/W-0x000x00x00x1
Table 7-49 ADC_DITH Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0x00Reserved
2ADC_DITH_ERRR/W0x0Small rounding errors may occur when subtracting the dither signal. The error can be chosen to either slightly degrade SNR or to slightly increase the DC offset and FS/2 spur. In addition, the FS/4 spur will also be increased slightly while in single channel mode.
0 : Rounding error degrades SNR
1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur
1ADC_DITH_AMPR/W0x00 : Small dither for better SNR (default)
1 : Large dither for better spurious performance
0ADC_DITH_ENR/W0x1Set this bit to enable ADC dither. Dither can improve spurious performance at the expense of slightly degraded SNR. The dither amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR and spurious performance.

7.6.1.31 Timing Adjustment for Bank 0 (0° Clock) Register (Address = 0x102) [reset = Undefined]

B0_TIME_0 is shown in Figure 7-37 and described in Table 7-50.

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Timing Adjustment for Bank 0 (0° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 0 ADC when ADC A is configured for a 0° clock phase (dual channel mode).

Figure 7-37 B0_TIME_0 Register
76543210
B0_TIME_0
R/W-Undefined
Table 7-50 B0_TIME_0 Register Field Descriptions
BitFieldTypeResetDescription
7-0B0_TIME_0R/WUndefined

Timing adjustment for bank 0 when ADC A is configured for 0° clock phase (dual channel mode).

7.6.1.32 Timing Adjustment for Bank 0 (90° Clock) Register (Address = 0x103) [reset = Undefined]

B0_TIME_90 is shown in Figure 7-38 and described in Table 7-51.

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Timing Adjustment for Bank 0 (–90° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 0 ADC when ADC A is configured for a –90° clock phase (single channel mode).

Figure 7-38 B0_TIME_90 Register
76543210
B0_TIME_90
R/W-Undefined
Table 7-51 B0_TIME_90 Register Field Descriptions
BitFieldTypeResetDescription
7-0B0_TIME_90R/WUndefined

Time adjustment for bank 0 applied when ADC is configured for –90° clock phase (single channel mode).

7.6.1.33 Timing Adjustment for Bank 1 (0° Clock) Register (Address = 0x112) [reset = Undefined]

B1_TIME_0 is shown in Figure 7-39 and described in Table 7-52.

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Timing Adjustment for Bank 1 (0° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 1 ADC when ADC A is configured for a 0° clock phase (dual channel mode).

Figure 7-39 B1_TIME_0 Register
76543210
B1_TIME_0
R/W-Undefined
Table 7-52 B1_TIME_0 Register Field Descriptions
BitFieldTypeResetDescription
7-0B1_TIME_0R/WUndefined

Timing adjustment for bank 1 applied when ADC is configured for 0° clock phase (dual channel mode).

7.6.1.34 Timing Adjustment for Bank 1 (90° Clock) Register (Address = 0x113) [reset = Undefined]

B1_TIME_90 is shown in Figure 7-40 and described in Table 7-53.

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Timing Adjustment for Bank 1 (–90° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 1 ADC when ADC A is configured for a –90° clock phase (single channel mode).

Figure 7-40 B1_TIME_90 Register
76543210
B1_TIME_90
R/W-Undefined
Table 7-53 B1_TIME_90 Register Field Descriptions
BitFieldTypeResetDescription
7-0B1_TIME_90R/WUndefined

Time adjustment for bank 1 applied when ADC is configured for –90° clock phase (single channel mode).

7.6.1.35 Timing Adjustment for Bank 4 (0° Clock) Register (Address = 0x142) [reset = Undefined]

B4_TIME_0 is shown in Figure 7-41 and described in Table 7-54.

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Timing Adjustment for Bank 4 (0° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 4 ADC when ADC B is configured for a 0° clock phase (dual channel mode and single channel mode).

Figure 7-41 B4_TIME_0 Register
76543210
B4_TIME_0
R/W-Undefined
Table 7-54 B4_TIME_0 Register Field Descriptions
BitFieldTypeResetDescription
7-0B4_TIME_0R/WUndefined

Timing adjustment for bank 4 applied when ADC is configured for 0° clock phase (dual channel mode and single channel mode).

7.6.1.36 Timing Adjustment for Bank 5 (0° Clock) Register (Address = 0x152) [reset = Undefined]

B5_TIME_0 is shown in Figure 7-42 and described in Table 7-55.

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Timing Adjustment for Bank 5 (0° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 5 ADC when ADC B is configured for a 0° clock phase (dual channel mode and single channel mode).

Figure 7-42 B5_TIME_0 Register
76543210
B5_TIME_0
R/W-Undefined
Table 7-55 B5_TIME_0 Register Field Descriptions
BitFieldTypeResetDescription
7-0B5_TIME_0R/WUndefined

Timing adjustment for bank 5 applied when ADC is configured for 0° clock phase (dual channel mode and single channel mode).

7.6.1.37 LSB_CTRL Register (Address = 0x160) [reset = 0x00]

LSB_CTRL is shown in Figure 7-43 and described in Table 7-56.

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LSB Control Bit Output register (default: 0x00). This register enables output of the timestamp signal on the LSB of the output samples.

Figure 7-43 LSB_CTRL Register
76543210
RESERVEDTIME_STAMP_EN
R/W-0x0R/W-0x0
Table 7-56 LSB_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0Reserved
0TIME_STAMP_ENR/W0x0

When set, the timestamp signal is transmitted on the LSB of the output samples. The latency of the timestamp signal (through the entire chip) matches the latency of the analog ADC inputs.

Also set TMSTP_RECV_EN when using TIME_STAMP_EN.

7.6.1.38 LSB_SEL Register (Address = 0x161) [reset = 0x00]

LSB_SEL is shown in Figure 7-44 and described in Table 7-57.

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LSB Control Bit Position register (default: 0x00). This register defines the position of the timestamp signal output on the LSB of the samples.

Figure 7-44 LSB_SEL Register
76543210
RESERVEDLSB_SEL
R/W-0x0R/W-0x0
Table 7-57 LSB_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0LSB_SELR/W0x0

0 : Place timestamp on lane 0 (Dx0±) of each LVDS output bus, independent of the LWIDTH setting. Lane 0 of each bus is enabled regardless of LWIDTH.
1 : Place timestamp on the LSB of the effective sample size as set by the LWIDTH parameter. The timestamp is placed on the LSB of the output sample. The lane that carries timestamp depends on the selected output sample width (LWIDTH).
For 12-bit samples, lane 0 carries the control data.
For 11-bit samples, lane 1 carries the control data.
For 10-bit samples, lane 2 carries the control data.
For 8-bit samples, lane 4 carries the control data.

7.6.1.39 UPAT0 Register (Address = 0x180) [reset = 0x0000]

UPAT0 is shown in Figure 7-45 and described in Table 7-58.

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User-Defined Pattern (sample 0) register (default: 0x0000). This register, and the UPATx registers that follow, define the user defined test pattern that can be used to test various aspects of the LVDS interface.

Figure 7-45 UPAT0 Register
15141312111098
RESERVEDUPAT0
R/W-0x0R/W-0x0
76543210
UPAT0
R/W-0x0
Table 7-58 UPAT0 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0x0

Reserved

11-0UPAT0R/W0x0

Defines the value for sample 0 of the user defined pattern. See the PAT_SEL register and the Section 7.4.5.6 section.
Note: Only change this register when LVDS_EN = 0.

7.6.1.40 UPAT1 Register (Address = 0x182) [reset = 0x0FFF]

UPAT1 is shown in Figure 7-46 and described in Table 7-59.

Return to Summary Table.

User-Defined Pattern (sample 1) register (default: 0x0FFF).

Figure 7-46 UPAT1 Register
15141312111098
RESERVEDUPAT1
R/W-0x0R/W-0xF
76543210
UPAT1
R/W-0xFF
Table 7-59 UPAT1 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0x0

Reserved

11-0UPAT1R/W0xFFF

Defines the value for sample 1 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

7.6.1.41 UPAT2 Register (Address = 0x184) [reset = 0x0000]

UPAT2 is shown in Figure 7-47 and described in Table 7-60.

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User-Defined Pattern (sample 2) register (default: 0x0000).

Figure 7-47 UPAT2 Register
15141312111098
RESERVEDUPAT2
R/W-0x0R/W-0x0
76543210
UPAT2
R/W-0x00
Table 7-60 UPAT2 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0x0

Reserved

11-0UPAT2R/W0x000

Defines the value for sample 2 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

7.6.1.42 UPAT3 Register (Address = 0x186) [reset = 0x0FFF]

UPAT3 is shown in Figure 7-48 and described in Table 7-61.

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User-Defined Pattern (sample 3) register (default: 0x0FFF)

Figure 7-48 UPAT3 Register
15141312111098
RESERVEDUPAT3
R/W-0x0R/W-0xF
76543210
UPAT3
R/W-0xFF
Table 7-61 UPAT3 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0x0Reserved
11-0UPAT3R/W0xFFF

Defines the value for sample 3 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

7.6.1.43 UPAT4 Register (Address = 0x188) [reset = 0x0000]

UPAT4 is shown in Figure 7-49 and described in Table 7-62.

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User-Defined Pattern (sample 4) register (default: 0x0000).

Figure 7-49 UPAT4 Register
15141312111098
RESERVEDUPAT4
R/W-0x0R/W-0x0
76543210
UPAT4
R/W-0x00
Table 7-62 UPAT4 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0x0

Reserved

11-0UPAT4R/W0x000

Defines the value for sample 4 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

7.6.1.44 UPAT5 Register (Address = 0x18A) [reset = 0x0FFF]

UPAT5 is shown in Figure 7-50 and described in Table 7-63.

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User-Defined Pattern (sample 5) register (default: 0x0FFF).

Figure 7-50 UPAT5 Register
15141312111098
RESERVEDUPAT5
R/W-0x0R/W-0xF
76543210
UPAT5
R/W-0xFF
Table 7-63 UPAT5 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0x0

Reserved

11-0UPAT5R/W0xFFF

Defines the value for sample 5 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

7.6.1.45 UPAT6 Register (Address = 0x18C) [reset = 0x0000]

UPAT6 is shown in Figure 7-51 and described in Table 7-64.

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User-Defined Pattern (sample 6) register (default: 0x0000).

Figure 7-51 UPAT6 Register
15141312111098
RESERVEDUPAT6
R/W-0x0R/W-0x0
76543210
UPAT6
R/W-0x00
Table 7-64 UPAT6 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0x0

Reserved

11-0UPAT6R/W0x000

Defines the value for sample 6 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

7.6.1.46 UPAT7 Register (Address = 0x18E) [reset = 0x0FFF]

UPAT7 is shown in Figure 7-52 and described in Table 7-65.

Return to Summary Table.

User-Defined Pattern (sample 7) register (default: 0x0FFF).

Figure 7-52 UPAT7 Register
15141312111098
RESERVEDUPAT7
R/W-0x0R/W-0xF
76543210
UPAT7
R/W-0xFF
Table 7-65 UPAT7 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0x0

Reserved

11-0UPAT7R/W0xFFF

Defines the value for sample 7 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

7.6.1.47 UPAT_CTRL Register (Address = 0x190) [reset = 0x1E]

UPAT_CTRL is shown in Figure 7-53 and described in Table 7-66.

Return to Summary Table.

User-Defined Pattern Control register (default: 0x1E). This register allows selection of the predefined lane pattern instead of the user defined pattern and the inversion of specified bits for each lane during user defined pattern transmission.

Figure 7-53 UPAT_CTRL Register
76543210
RESERVEDLANE_PATUPAT_INV_DUPAT_INV_CUPAT_INV_BUPAT_INV_A
R/W-0x0R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x0
Table 7-66 UPAT_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0x0

Reserved

4LANE_PATR/W0x1

When set, the UPATn registers are ignored, and the user-defined pattern is set to: 0x000, 0xFFF, 0x000, 0x000, 0x000, 0xFFF, 0xFFF, 0xFFF. This bit acts as a shortcut to avoid programming the UPATn registers. PAT_SEL register must still be programmed to configure the interface to select the user-defined pattern. The UPAT_INV_* registers still apply when using LANE_PAT.

3UPAT_INV_DR/W0x1

When set, bit [11] of the user-defined pattern is inverted on the bus D output.

2UPAT_INV_CR/W0x1

When set, bit [10] of the user-defined pattern is inverted on the bus C output.

1UPAT_INV_BR/W0x1

When set, bit [9] of the user-defined pattern is inverted on the bus B output.

0UPAT_INV_AR/W0x0

When set, bit [8] of the user-defined pattern is inverted on the bus A output.

Note: Only change this register when LVDS_EN = 0.

7.6.1.48 LVDS_EN Register (Address = 0x200) [reset = 0x01]

LVDS_EN is shown in Figure 7-54 and described in Table 7-67.

Return to Summary Table.

LVDS Subsystem Enable register (default: 0x01). Use this register to enable or disable the LVDS interface.

Figure 7-54 LVDS_EN Register
76543210
RESERVEDLVDS_EN
R/W-0x0R/W-0x1
Table 7-67 LVDS_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0LVDS_ENR/W0x1

0 : Disable LVDS interface
1 : Enable LVDS interface

Note 1: Before altering other LVDS registers, you must clear LVDS_EN. When LVDS_EN is 0, the LVDS interface block is held in reset and the outputs are powered down. The clocks are gated off to save power. The frame counter is also held in reset, so SYSREF will not align the frame counter.

Note 2: Always set CAL_EN before setting LVDS_EN.
Note 3: Always clear LVDS_EN before clearing CAL_EN.

7.6.1.49 LMODE Register (Address = 0x201) [reset = 0x01]

LMODE is shown in Figure 7-55 and described in Table 7-68.

Return to Summary Table.

LVDS Mode register (default: 0x01). This register is used to define the configuration of the LVDS interface. LVDS_EN must be 0 before making any changes to this register. Additionally, CAL_EN must be 0 before changing DES_EN.

Figure 7-55 LMODE Register
76543210
RESERVEDLWIDTHRESERVEDDES_ENLALIGNEDLDEMUX
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x1
Table 7-68 LMODE Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0x0

Reserved

5-4LWIDTHR/W0x0

Specifies the sample width for the LVDS output interface.
0 : 12-bit sample width (default)
1 : 11-bit sample width
2 : 10-bit sample width
3 : 8-bit sample width

3RESERVEDR/W0x0

Reserved

2DES_ENR/W0x0

0 : Disable DES mode (enable dual channel mode)
1 : Enable DES mode (enable single channel mode)
CAL_EN must be 0 before changing DES_EN.

1LALIGNEDR/W0x0

0 : The LVDS buses are staggered for optimized switching noise and latency.
1 : The LVDS buses are aligned for simplified timing.

0LDEMUXR/W0x1

0 : Demux-by-1, uses 2 LVDS buses total
1 : Demux-by-2, uses 4 LVDS buses total

7.6.1.50 LFRAME Register (Address = 0x202) [reset = 0x80]

LFRAME is shown in Figure 7-56 and described in Table 7-69.

Return to Summary Table.

LVDS Frame Length register (default: 0x80) (128 decimal). This register sets the length of the frame and subsequently the period of the strobe signal. Only change this register when LVDS_EN = 0.

Figure 7-56 LFRAME Register
76543210
LFRAME
R/W-0x80
Table 7-69 LFRAME Register Field Descriptions
BitFieldTypeResetDescription
7-0LFRAMER/W0x80

Defines the number of UIs in each LVDS frame. Any multiple of 4 from 4 to 128 is supported. All other values are unsupported.

When LDEMUX=0, one UI is one CLK± cycle.
When LDEMUX=1, one UI is two CLK± cycles.

Note: Setting LFRAME to 4 is not recommended, as it may be difficult to achieve deterministic latency over all process, voltage, and temperature conditions. The propagation delay variation may be larger than the frame period.

7.6.1.51 LSYNC_N Register (Address = 0x203) [reset = 0x01]

LSYNC_N is shown in Figure 7-57 and described in Table 7-70.

Return to Summary Table.

LVDS Manual Sync Request register (default: 0x01). This register can be used as a software replacement for the LVDS SYNC signal.

Figure 7-57 LSYNC_N Register
76543210
RESERVEDLSYNC_N
R/W-0x0R/W-0x1
Table 7-70 LSYNC_N Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0LSYNC_NR/W0x1

Set this bit to 0 to request LVDS synchronization (equivalent to the hardware SYNC signal being asserted, as selected by SYNC_SEL). For normal operation, leave this bit set to 1.

Note: The LSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL setting in the LCTRL register. However, if the selected sync pin is stuck low, the synchronization request cannot be de-asserted unless SYNC_SEL=2.

7.6.1.52 LCTRL Register (Address = 0x204) [reset = 0x02]

LCTRL is shown in Figure 7-58 and described in Table 7-71.

Return to Summary Table.

LVDS Control register (default: 0x02). This register is used to configure aspects of the LVDS interface including scrambling, hardware SYNC input and the output format. Only change this register when LVDS_EN = 0.

Figure 7-58 LCTRL Register
76543210
RESERVEDSCRSYNC_SELSFORMATRESERVED
R/W-0x0R/W-0x0R/W-0x0R/W-0x1R/W-0x0
Table 7-71 LCTRL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0x0

Reserved

4SCRR/W0x0

When set, all LVDS data and strobes are scrambled. This also includes the part-time strobes or timestamp signals (since they are output on the data lanes). See the Section 7.4.5.5 section.

3-2SYNC_SELR/W0x0

0 : Use the SYNC_SE input for SYNC function (default)
1 : Use the TMSTP± input for SYNC function. also set TMSTP_RECV_EN to use the differential TMSTP± input.
2 : Do not use any SYNC input pin, set if using LSYNC_N.

1SFORMATR/W0x1

Output sample format for LVDS output samples
0 : Offset binary
1 : Signed 2’s complement (default)

0RESERVEDR/W0x0Reserved

7.6.1.53 PAT_SEL Register (Address = 0x205) [reset = 0x02]

PAT_SEL is shown in Figure 7-59 and described in Table 7-72.

Return to Summary Table.

LVDS Pattern Control register (default: 0x02). This register controls the output data or pattern used during active mode ( SYNC de-asserted) and sync mode ( SYNC asserted). During normal operation, the active pattern should be set to the ADC output data and the SYNC pattern can be set to the mode used by the receiver for synchronizing the interface. The input used for SYNC is chosen by SYNC_SEL.

Figure 7-59 PAT_SEL Register
76543210
ACT_PATSYNC_PAT
R/W-0x0R/W-0x2
Table 7-72 PAT_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-4ACT_PATR/W0x0

This selects the output pattern that is generated when the SYNC signal is de-asserted.

0: ADC output data
1: All LVDS lanes output the user-defined pattern (see UPAT registers)
2-15: Reserved

3-0SYNC_PATR/W0x2

This selects the output pattern that is generated when the SYNC signal is asserted.

0: Reserved
1: All LVDS lanes output the user-defined pattern (see UPAT registers)
2: Frame strobe is transmitted on the LSB of the output samples only. The other bits transmit data based on ACT_PAT.
3: The frame strobe is transmitted on all active LVDS data lanes and strobes.
4-15: Reserved

7.6.1.54 LCS_EN Register (Address = 0x206) [reset = 0xFF]

LCS_EN is shown in Figure 7-60 and described in Table 7-73.

Return to Summary Table.

LVDS Clock and Strobe Enables register (default: 0xFF). Use these registers to enable or disable specific LVDS output clocks (DxCLK±) and frame strobes (DxSTB±) if the receiver will not use them. If an entire LVDS bus is disabled (because of PD_CH or LDEMUX) then its associated clock and frame strobe are disabled automatically, regardless of this register. Note: Only change this register when LVDS_EN = 0.

Figure 7-60 LCS_EN Register
76543210
DDSTB_ENDCSTB_ENDBSTB_ENDASTB_ENDDCLK_ENDCCLK_ENDBCLK_ENDACLK_EN
R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1
Table 7-73 LCS_EN Register Field Descriptions
BitFieldTypeResetDescription
7DDSTB_ENR/W0x1

Enable DDSTB± output

6DCSTB_ENR/W0x1

Enable DCSTB± output

5DBSTB_ENR/W0x1

Enable DBSTB± output

4DASTB_ENR/W0x1

Enable DASTB± output

3DDCLK_ENR/W0x1

Enable DDCLK± output

2DCCLK_ENR/W0x1

Enable DCCLK± output

1DBCLK_ENR/W0x1

Enable DBCLK± output

0DACLK_ENR/W0x1

Enable DACLK± output

7.6.1.55 LVDS_STATUS Register (Address = 0x208) [reset = Undefined]

LVDS_STATUS is shown in Figure 7-61 and described in Table 7-74.

Return to Summary Table.

System Status register (default: undefined). This register returns status bits for the device including SYNC status for the LVDS interface and internal clock status.

Figure 7-61 LVDS_STATUS Register
76543210
RESERVEDSYNC_STATUSREALIGNEDALIGNEDRESERVED
R/W-0x0R/W-UndefinedR/W-UndefinedR/W-UndefinedR/W-0x0
Table 7-74 LVDS_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0x0Reserved
5SYNC_STATUSR/WUndefined

Returns the instantaneous state of the LVDS interface SYNC signal ( SYNC_SE or TMSTP±).
0 : SYNC asserted
1 : SYNC de-asserted

4REALIGNEDR/WUndefined

When high, indicates that SYSREF realigned internal clocks. REALIGNED_ALM should be used for monitoring of realignment events instead of this bit. Writing a 1 to this bit will clear it, but will not affect the REALIGNED_ALM bit.

3ALIGNEDR/WUndefined

When high, indicates that internal clock phases have been established by SYSREF. Any SYSREF rising edge that is processed after enabling the LVDS system will set this bit. This bit can be monitored during startup to verify that SYSREF has been processed before continuing system initialization. Writing a 1 to this bit will clear it and the next SYSREF event will set it again.

2-0RESERVEDR/W0x0Reserved

7.6.1.56 PD_CH Register (Address = 0x209) [reset = 0x00]

PD_CH is shown in Figure 7-62 and described in Table 7-75.

Return to Summary Table.

ADC Channel Power Down (default: 0x00). This register allows individual channels to be powered down. LVDS_EN and CAL_EN must be set to 0 before changing PD_CH.

Figure 7-62 PD_CH Register
76543210
RESERVEDPD_BCHPD_ACH
R/W-0x0R/W-0x0R/W-0x0
Table 7-75 PD_CH Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0x0

Reserved

1PD_BCHR/W0x0

When set, the “B” ADC channel is powered down.

0PD_ACHR/W0x0

When set, the “A” ADC channel is powered down.

Important notes:
LVDS_EN and CAL_EN must be set to 0 before changing PD_CH.
PD_CH disables the LVDS lanes (Dx[11:0], DxSTB, DxCLK) for the powered down channel.
To power down both ADC channels, use MODE or the PD pin.

7.6.1.57 OVR_T0 Register (Address = 0x211) [reset = 0xF2]

OVR_T0 is shown in Figure 7-63 and described in Table 7-76.

Return to Summary Table.

Overrange Threshold 0 register (default: 0xF2). This register sets threshold 0 for ADC overrange detection.

Figure 7-63 OVR_T0 Register
76543210
OVR_T0
R/W-0xF2
Table 7-76 OVR_T0 Register Field Descriptions
BitFieldTypeResetDescription
7-0OVR_T0R/W0xF2

This parameter defines the absolute sample level that causes OVA0 or OVB0 to be set. The detection level in dBFS (peak) is 20log10(OVR_T0/256) (default: 0xF2 = 242 –> -0.5dBFS)

7.6.1.58 OVR_T1 Register (Address = 0x212) [reset = 0xAB]

OVR_T1 is shown in Figure 7-64 and described in Table 7-77.

Return to Summary Table.

Overrange Threshold 1 register (default: 0xAB). This register sets threshold 1 for ADC overrange detection.

Figure 7-64 OVR_T1 Register
76543210
OVR_T1
R/W-0xAB
Table 7-77 OVR_T1 Register Field Descriptions
BitFieldTypeResetDescription
7-0OVR_T1R/W0xAB

This parameter defines the absolute sample level that causes OVA1 or OVB1 to be set. The detection level in dBFS (peak) is 20log10(OVR_T1/256) (default: 0xAB = 171 –> -3.5dBFS)

7.6.1.59 OVR_CFG Register (Address = 0x213) [reset = 0x07]

OVR_CFG is shown in Figure 7-65 and described in Table 7-78.

Return to Summary Table.

Overrange Enable/Hold Off register (default: 0x07). This register enables overrange detection and sets the output pulse duration for an overrange event. The maximum overrange pulse duration is recommended to avoid excess switching noise.

Figure 7-65 OVR_CFG Register
76543210
RESERVEDOVR_ENOVR_N
R/W-0x0R/W-0x0R/W-0x7
Table 7-78 OVR_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0x0

Reserved

3OVR_ENR/W0x0

ORA0, ORA1, ORB0 and ORB1 outputs pins are enabled and output the overrange status when this bit is set high. The outputs are held low when this bit is set low.

2-0OVR_NR/W0x7

Program this register to adjust the pulse length for the ORA0, ORA1 and ORB0, ORB1 outputs.
The minimum pulse duration of the overrange outputs is 8 × 2OVR_N CLK± cycles.

7.6.1.60 SPIN_ID Register (Address = 0x297) [reset = 0x00]

SPIN_ID is shown in Figure 7-66 and described in Table 7-79.

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Chip Spin Identifier register (default from fuse ROM, read-only). This register returns the spin identification number of the device.

Figure 7-66 SPIN_ID Register
76543210
RESERVEDSPIN_ID
R/W-0x0R/W-0x0
Table 7-79 SPIN_ID Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0x0

Reserved

4-0SPIN_IDR/W0x0

Returns 0 to indicate that this device is ADC12DL3200.

7.6.1.61 SRC_EN Register (Address = 0x2B0) [reset = 0x00]

SRC_EN is shown in Figure 7-67 and described in Table 7-80.

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SYSREF Calibration Enable register (default: 0x00). This register starts the SYSREF calibration process.

Figure 7-67 SRC_EN Register
76543210
RESERVEDSRC_EN
R/W-0x0R/W-0x0
Table 7-80 SRC_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0x0

Reserved

0SRC_ENR/W0x0

0 : SYSREF calibration disabled (default). Use the TAD register to manually control the tAD Adjust setting and adjust the CLK± aperture delay.
1: SYSREF calibration enabled. The CLK± delay is automatically calibrated. The TAD register is ignored. A 0-to-1 transition on SRC_EN starts the SYSREF calibration sequence. Program SRC_CFG before setting SRC_EN. Ensure that ADC calibration is not running before setting SRC_EN.

7.6.1.62 SRC_CFG Register (Address = 0x2B1) [reset = 0x05]

SRC_CFG is shown in Figure 7-68 and described in Table 7-81.

Return to Summary Table.

SYSREF Calibration Configuration register (default: 0x05). This register determines the amount of averaging performed for automatic SYSREF calibration and sets the maximum supported SYSREF cycle. The total duration of SYSREF calibration will be no longer than: TSYSREFCAL (in CLK± cycles) = 256 * 19 * 4 * (SRC_AVG + SRC_HDUR + 2).

Figure 7-68 SRC_CFG Register
76543210
RESERVEDSRC_AVGSRC_HDUR
R/W-0x0R/W-0x1R-0x1
Table 7-81 SRC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0x0Reserved
3-2SRC_AVGR/W0x1

Specifies the amount of averaging used for SYSREF Calibration. Larger values will increase calibration time and reduce the variance of the calibrated value.

0: 4 high-speed accumulations for each SYSREF measurement
1: 16 high-speed accumulations for each SYSREF measurement
2: 64 high-speed accumulations for each SYSREF measurement
3: 256 high-speed accumulations for each SYSREF measurement

1-0SRC_HDURR/W0x1

Specifies the duration of each high-speed accumulation for SYSREF Calibration. If the SYSREF period exceeds the supported value, calibration will fail. Larger values will increase calibration time and support longer SYSREF periods. For a given SYSREF period, larger values will also reduce the variance of the calibrated value.

0: 4 cycles per accumulation, supporting SYSREF periods of up to 85 CLK± cycles
1: 16 cycles per accumulation, supporting SYSREF periods of up to 1100 CLK± cycles
2: 64 cycles per accumulation, supporting SYSREF periods of up to 5200 CLK± cycles
3: 256 cycles per accumulation, supporting SYSREF periods of up to 21580 CLK± cycles

7.6.1.63 SRC_STATUS Register (Address = 0x2B2) [reset = Undefined]

SRC_STATUS is shown in Figure 7-69 and described in Table 7-82.

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SYSREF Calibration Status register (read-only, default: undefined). This register indicates that the SYSREF calibration process has completed and outputs the result of the SYSREF calibration process.

Figure 7-69 SRC_STATUS Register
2322212019181716
RESERVEDSRC_DONESRC_TAD[16]
R-UndefinedR-UndefinedR-Undefined
15141312111098
SRC_TAD[15:8]
R-Undefined
76543210
SRC_TAD[7:0]
R-Undefined
Table 7-82 SRC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
23-18RESERVEDR/W0x0

Reserved

17SRC_DONER/W0x0

This bit returns ‘1’ when SRC_EN=1 and SYSREF Calibration has been completed.

16-0SRC_TADR/W0x0

This field returns the value for t AD Adjust computed by SYSREF Calibration. It is only valid if SRC_DONE=1. SRC_TAD[16] indicates if CLK± has been inverted. SRC_TAD[15:8] indicates the coarse delay adjustment.
SRC_TAD[7:0] indicates the fine delay adjustment. SRC_TAD can be read out and manually written to the TAD register during subsequent boot cycles for repeatability.

7.6.1.64 TAD Register (Address = 0x2B5-2B7) [reset = 0x000000]

TAD is shown in Figure 7-70 and described in Table 7-83.

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CLK± Timing Adjust register (default: 0x00). This register sets the tAD Adjust delay when automatic SYRSEF calibration is not used.

Figure 7-70 TAD Register
2322212019181716
RESERVEDTAD[16]
R-UndefinedR-0x0
15141312111098
TAD[15:8]
R-0x00
76543210
TAD[7:0]
R-0x00
Table 7-83 TAD Register Field Descriptions
BitFieldTypeResetDescription
23-17RESERVEDR/W0x0Reserved
16-0TADR/W0x0

This register controls tAD Adjust when SRC_EN=0. Use this register to manually control the CLK± inversion and delay when SYSREF Calibration is disabled.

TAD[16] inverts CLK± when set. TAD[15:8] controls the coarse delay adjustment. TAD[7:0] controls the fine delay adjustment.

If ADC calibration is enabled (CAL_EN=1), or the LVDS interface is enabled (LVDS_EN=1), the following rules must be obeyed to avoid clock glitches and unpredictable behavior:
Do not change TAD[16]. CAL_EN and LVDS_EN must be set to 0 before changing TAD[16].
TAD[15:8] must be increased or decreased gradually (no more than 4 codes at a time). This rule can be obeyed manually via SPI writes or by setting TAD_RAMP_EN.
TAD[7:0] may be changed to any value at any time since its resolution is too fine to cause clock glitches.

7.6.1.65 TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]

TAD_RAMP is shown in Figure 7-71 and described in Table 7-84.

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CLK± Timing Adjust Ramp Control register (default: 0x00). This register enables the tAD adjust ramping feature and sets the ramp rate.

Figure 7-71 TAD_RAMP Register
76543210
RESERVEDTAD_RAMP_RATETAD_RAMP_EN
R/W-0x0R/W-0x0R/W-0x0
Table 7-84 TAD_RAMP Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0x0

Reserved

1TAD_RAMP_RATER/W0x0

Specify the ramp rate for tAD adjust when the TAD[15:8] register is written while TAD_RAMP_EN is 1.
0 : tAD adjust ramps up or down one code per 256 CLK± cycles.
1 : tAD adjust ramps up or down four codes per 256 CLK± cycles.

0TAD_RAMP_ENR/W0x0

TAD ramp enable. Set this bit if ramping of the coarse tAD adjust is desired.
0 : After writing the TAD[15:8] register, tAD adjust is updated fully within 1024 CLK± cycles (ramp feature disabled).
1 : After writing the TAD[15:8] register, tAD adjust ramps up or down gradually until it matches the TAD[15:8] register.

When TAD_RAMP_EN is 1, and the user writes the TAD[15:8] register, a digital counter will automatically ramp tAD adjust up or down until it matches the TAD[15:8] register value. This ensures that the coarse delay changes gradually and does not cause glitches in the delayed CLK± waveform.

7.6.1.66 ALARM Register (Address = 0x2C0) [reset = Undefined]

ALARM is shown in Figure 7-72 and described in Table 7-85.

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Alarm Interrupt register (read-only). This register indicates if any unmasked alarm in has been triggered in the ALM_STATUS register.

Figure 7-72 ALARM Register
76543210
RESERVEDALARM
R-UndefinedR-Undefined
Table 7-85 ALARM Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDRUndefined

Reserved

0ALARMRUndefined

This bit returns a ‘1’ whenever any unmasked alarm is set in the ALM_STATUS register. Use ALM_MASK to mask (disable) individual alarms.
CAL_STATUS_SEL can be used to drive the ALARM bit onto the CAL_STAT pin to provide a hardware alarm interrupt signal.

7.6.1.67 ALM_STATUS Register (Address = 0x2C1) [reset = 0x05]

ALM_STATUS is shown in Figure 7-73 and described in Table 7-86.

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Alarm Status register (default: 0x05, write to clear). This register indicates if the individual alarms have been triggered.

Figure 7-73 ALM_STATUS Register
76543210
RESERVEDREALIGNED_ALMRESERVEDCLK_ALM
R/W-0x0R/W-0x1R/W-0x0R/W-0x1
Table 7-86 ALM_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0x0

Reserved

2REALIGNED_ALMR/W0x1

Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the frame counter) to be realigned to a new phase. Write a ‘1’ to clear this bit.

1RESERVEDR/W0x0

Reserved

0CLK_ALMR/W0x1

Clock Alarm: This bit can be used to detect an upset to the internal clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match. Write a ‘1’ to clear this bit. Refer to Alarm Monitoring for the proper usage of this register.

Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’

7.6.1.68 ALM_MASK Register (Address = 0x2C2) [reset = 0x05]

ALM_MASK is shown in Figure 7-74 and described in Table 7-87.

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Alarm Mask register (default: 0x05). This register is used to mask out alarms that should not trigger the ALARM interrupt.

Figure 7-74 ALM_MASK Register
76543210
RESERVEDMASK_REALIGNED_ALMRESERVEDMASK_CLK_ALM
R/W-0x0R/W-0x1R/W-0x0R/W-0x1
Table 7-87 ALM_MASK Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0x0

Reserved

2MASK_REALIGNED_ALMR/W0x1

When set, REALIGNED_ALM is masked and will not impact the ALARM register bit.

1RESERVEDR/W0x0

Reserved

0MASK_CLK_ALMR/W0x1

When set, CLK_ALM is masked and will not impact the ALARM register bit.

7.6.1.69 TADJ_A Register (Address = 0x310) [reset = Undefined]

TADJ_A is shown in Figure 7-75 and described in Table 7-88.

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Timing Adjust for A-ADC, Dual Mode register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information.

Figure 7-75 TADJ_A Register
76543210
TADJ_A
R/W-Undefined
Table 7-88 TADJ_A Register Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_AR/WUndefined

This register (and other TADJ* registers that follow it) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes of operation.

The default values for all TADJ* registers are loaded from the fuse ROM. The factory trimmed values can be read out and adjusted as required.

7.6.1.70 TADJ_B Register (Address = 0x313) [reset = Undefined]

TADJ_B is shown in Figure 7-76 and described in Table 7-89.

Return to Summary Table.

Timing Adjust for B-ADC, Dual Mode register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information.

Figure 7-76 TADJ_B Register
76543210
TADJ_B
R/W-Undefined
Table 7-89 TADJ_B Register Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_BR/WUndefinedSee TADJ_A register for description.

7.6.1.71 TADJ_A_FG90_VINA Register (Address = 0x314) [reset = Undefined]

TADJ_A_FG90_VINA is shown in Figure 7-77 and described in Table 7-90.

Return to Summary Table.

Timing Adjust for A-ADC, DES, Foreground Calibration, INA± register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information.

Figure 7-77 TADJ_A_FG90_VINA Register
76543210
TADJ_A_FG90_VINA
R/W-Undefined
Table 7-90 TADJ_A_FG90_VINA Register Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_A_FG90_VINAR/WUndefinedSee TADJ_A register for description.

7.6.1.72 TADJ_B_FG0_VINA Register (Address = 0x315) [reset = Undefined]

TADJ_B_FG0_VINA is shown in Figure 7-78 and described in Table 7-91.

Return to Summary Table.

Timing Adjust for B-ADC, DES, Foreground Calibration, INA± regsiter (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information.

Figure 7-78 TADJ_B_FG0_VINA Register
76543210
TADJ_B_FG0_VINA
R/W-Undefined
Table 7-91 TADJ_B_FG0_VINA Register Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_B_FG0_VINAR/WUndefinedSee TADJ_A register for description.

7.6.1.73 TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = Undefined]

TADJ_A_FG90_VINB is shown in Figure 7-79 and described in Table 7-92.

Return to Summary Table.

Timing Adjust for A-ADC, DES, Foreground Calibration, INB± register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information.

Figure 7-79 TADJ_A_FG90_VINB Register
76543210
TADJ_A_FG90_VINB
R/W-Undefined
Table 7-92 TADJ_A_FG90_VINB Register Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_A_FG90_VINBR/WUndefinedSee TADJ_A register for description.

7.6.1.74 TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]

TADJ_B_FG0_VINB is shown in Figure 7-80 and described in Table 7-93.

Return to Summary Table.

Timing Adjust for B-ADC, DES, Foreground Calibration, INB± register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information.

Figure 7-80 TADJ_B_FG0_VINB Register
76543210
TADJ_B_FG0_VINB
R/W-Undefined
Table 7-93 TADJ_B_FG0_VINB Register Field Descriptions
BitFieldTypeResetDescription
7-0TADJ_B_FG0_VINBR/WUndefinedSee TADJ_A register for description.

7.6.1.75 OADJ_A_FG0_VINA Register (Address = 0x344) [reset = Undefined]

OADJ_A_FG0_VINA is shown in Figure 7-81 and described in Table 7-94.

Return to Summary Table.

Offset Adjustment for A-ADC / Foreground Calibration / 0° Clock / INA± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details.

Figure 7-81 OADJ_A_FG0_VINA Register
15141312111098
RESERVEDOADJ_A_FG0_VINA
R/W-UndefinedR/W-Undefined
76543210
OADJ_A_FG0_VINA
R/W-Undefined
Table 7-94 OADJ_A_FG0_VINA Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/WUndefined

Reserved

11-0OADJ_A_FG0_VINAR/WUndefined

Offset adjustment value applied to A-ADC when it samples INA± using 0° clock phase and foreground calibration is enabled.

7.6.1.76 OADJ_A_FG0_VINB Register (Address = 0x346) [reset = Undefined]

OADJ_A_FG0_VINB is shown in Figure 7-82 and described in Table 7-95.

Return to Summary Table.

Offset Adjustment for A-ADC / Foreground Calibration / 0° Clock / INB± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details.

Figure 7-82 OADJ_A_FG0_VINB Register
15141312111098
RESERVEDOADJ_A_FG_VINB
R/W-UndefinedR/W-Undefined
76543210
OADJ_A_FG_VINB
R/W-Undefined
Table 7-95 OADJ_A_FG0_VINB Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/WUndefined

Reserved

11-0OADJ_A_FG0_VINBR/WUndefined

Offset adjustment value applied to A-ADC when it samples INB± using 0° clock phase and foreground calibration is enabled.

7.6.1.77 OADJ_A_FG90_VINA Register (Address = 0x348) [reset = Undefined]

OADJ_A_FG90_VINA is shown in Figure 7-83 and described in Table 7-96.

Return to Summary Table.

Offset Adjustment for A-ADC / Foreground Calibration / 90° Clock / INA± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details.

Figure 7-83 OADJ_A_FG90_VINA Register
15141312111098
RESERVEDOADJ_A_FG90_VINA
R/W-UndefinedR/W-Undefined
76543210
OADJ_A_FG90_VINA
R/W-Undefined
Table 7-96 OADJ_A_FG90_VINA Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/WUndefined

Reserved

11-0OADJ_A_FG90_VINAR/WUndefined

Offset adjustment value applied to A-ADC when it samples INA± using 90° clock phase and foreground calibration is enabled.

7.6.1.78 OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = Undefined]

OADJ_A_FG90_VINB is shown in Figure 7-84 and described in Table 7-97.

Return to Summary Table.

Offset Adjustment for A-ADC / Foreground Calibration / 90° Clock / INB± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details.

Figure 7-84 OADJ_A_FG90_VINB Register
15141312111098
RESERVEDOADJ_A_FG90_VINB
R/W-UndefinedR/W-Undefined
76543210
OADJ_A_FG90_VINB
R/W-Undefined
Table 7-97 OADJ_A_FG90_VINB Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/WUndefined

Reserved

11-0OADJ_A_FG90_VINBR/WUndefined

Offset adjustment value applied to A-ADC when it samples INB± using 90° clock phase and foreground calibration is enabled.

7.6.1.79 OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = Undefined]

OADJ_B_FG0_VINA is shown in Figure 7-85 and described in Table 7-98.

Return to Summary Table.

Offset Adjustment for B-ADC / Foreground Calibration / INA± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details.

Figure 7-85 OADJ_B_FG0_VINA Register
15141312111098
RESERVEDOADJ_B_FG0_VINA
R/W-UndefinedR/W-Undefined
76543210
OADJ_B_FG0_VINA
R/W-Undefined
Table 7-98 OADJ_B_FG0_VINA Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/WUndefined

Reserved

11-0OADJ_B_FG0_VINAR/WUndefined

Offset adjustment value applied to B-ADC when it samples INA± using 0° clock phase and foreground calibration is enabled.

7.6.1.80 OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = Undefined]

OADJ_B_FG0_VINB is shown in Figure 7-86 and described in Table 7-99.

Return to Summary Table.

Offset Adjustment for B-ADC / Foreground Calibration / INB± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details.

Figure 7-86 OADJ_B_FG0_VINB Register
15141312111098
RESERVEDOADJ_B_FG0_VINB
R/W-UndefinedR/W-Undefined
76543210
OADJ_B_FG0_VINB
R/W-Undefined
Table 7-99 OADJ_B_FG0_VINB Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/WUndefined

Reserved

11-0OADJ_B_FG0_VINBR/WUndefined

Offset adjustment value applied to B-ADC when it samples INB± using 0° clock phase and foreground calibration is enabled.

7.6.1.81 GAIN_B0 Register (Address = 0x360) [reset = Undefined]

GAIN_B0 is shown in Figure 7-87 and described in Table 7-100.

Return to Summary Table.

Fine Gain Adjust for Bank 0 register (default from fuse ROM). This register adjusts the gain of the Bank 0 ADC.

Figure 7-87 GAIN_B0 Register
76543210
RESERVEDGAIN_B0
R/W-UndefinedR/W-Undefined
Table 7-100 GAIN_B0 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/WUndefined

Reserved

4-0GAIN_B0R/WUndefined

Fine gain adjustment for bank 0.

7.6.1.82 GAIN_B1 Register (Address = 0x361) [reset = Undefined]

GAIN_B1 is shown in Figure 7-88 and described in Table 7-101.

Return to Summary Table.

Fine Gain Adjust for Bank 1 register (default from fuse ROM). This register adjusts the gain of the Bank 1 ADC.

Figure 7-88 GAIN_B1 Register
76543210
RESERVEDGAIN_B1
R/W-UndefinedR/W-Undefined
Table 7-101 GAIN_B1 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/WUndefined

Reserved

4-0GAIN_B1R/WUndefined

Fine gain adjustment for bank 1.

7.6.1.83 GAIN_B4 Register (Address = 0x364) [reset = Undefined]

GAIN_B4 is shown in Figure 7-89 and described in Table 7-102.

Return to Summary Table.

Fine Gain Adjust for Bank 4 register (default from fuse ROM). This register adjusts the gain of the Bank 4 ADC.

Figure 7-89 GAIN_B4 Register
76543210
RESERVEDGAIN_B4
R/W-UndefinedR/W-Undefined
Table 7-102 GAIN_B4 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/WUndefined

Reserved

4-0GAIN_B4R/WUndefined

Fine gain adjustment for bank 4.

7.6.1.84 GAIN_B5 Register (Address = 0x365) [reset = Undefined]

GAIN_B5 is shown in Figure 7-90 and described in Table 7-103.

Return to Summary Table.

Fine Gain Adjust for Bank 5 register (default from fuse ROM). This register adjusts the gain of the Bank 5 ADC.

Figure 7-90 GAIN_B5 Register
76543210
RESERVEDGAIN_B5
R/W-UndefinedR/W-Undefined
Table 7-103 GAIN_B5 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/WUndefined

Reserved

4-0GAIN_B5R/WUndefined

Fine gain adjustment for bank 5.