SLVSG41 January   2022 TPS7H4003-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjust UVLO
      7. 7.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 7.3.7.1 Internal Oscillator Mode
        2. 7.3.7.2 External Synchronization Mode
        3. 7.3.7.3 Primary-Secondary Operation Mode
      8. 7.3.8  Soft-Start (SS/TR)
      9. 7.3.9  Power Good (PWRGD)
      10. 7.3.10 Sequencing
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Overcurrent Protection
        1. 7.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Turn-On Behavior
      15. 7.3.15 Slope Compensation
        1. 7.3.15.1 Slope Compensation Requirements
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Output Schottky Diode
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Soft-Start Capacitor Selection
        7. 8.2.2.7 Undervoltage Lockout (UVLO) Set Point
        8. 8.2.2.8 Output Voltage Feedback Resistor Selection
          1. 8.2.2.8.1 Minimum Output Voltage
        9. 8.2.2.9 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8.2.3 Parallel Operation

The TPS7H4003-SEP can be configured in primary-secondary mode to provide up to 72-A output current. Figure 8-2 shows a parallel configuration that can be used to provide 36-A output.

Figure 8-2 Parallel Configuration Showing Primary and Secondary

The design procedure to configure the primary-secondary operation using the internal oscillator is as follows:

  • The RT pin of the primary device must be left floating. This achieves two purposes, to set the frequency to 500 kHz (typical) using the internal oscillator and to configure the SYNC1 and SYNC2 pins of the primary device as output pins with a 500-kHz clock, in-phase and 90° out of phase, respectively to the internal oscillator of the primary device. For more details, see Adjustable Switching Frequency and Synchronization (SYNC) section.
  • The RT pin on secondary device should be connected to a resistor such that the frequency of the secondary device matches the primary's frequency, 500 kHz in this case. See Figure 7-4 for reference.
  • SYNC1 and/or SYNC2 pin of the primary device must be connected to the SYNC1 pin of the secondary device(s).
  • Only a single feedback network is connected to the VSENSE pin of the primary device. Therefore, all VSENSE pins must be connected.
  • Only a single compensation network is needed connected to the COMP pin of the primary device. Therefore all COMP pins must be connected.
  • Only a single soft-start capacitor is needed connected to the SS pin of the primary device. Therefore all SS pins must be connected.
  • Only a single enable signal (or resistor divider) is needed connected to the EN pin of the primary device. Therefore all EN pins must be connected.
  • Since the primary device controls the compensation, soft-start and enable networks, the factor of n must be taken into account when calculating the components associated with these pins, where n is the number of devices in parallel.

The primary-secondary mode can also be implemented using an external clock. In such case, a different frequency other than 500 kHz can be used. When using an external clock, the RT and SYNC pin configurations vary as follows:

  • RT pins of both primary and secondary device must be connected to a resistor matching the frequency of the external clock being used. See Figure 7-4 for reference.
  • The external clock is connected to the SYNC1 pin of the primary device. A 10-kΩ resistor to GND should be connected to the SYNC1 pin as well.
  • For two devices in parallel, an inverted clock (180° out of phase respect to the primary device) must be connected to the SYNC1 pin of the secondary device. A 10-kΩ resistor to GND should be connected to the SYNC1 pin as well. The SYNC2 pins of the primary and secondary devices should be connected to VIN.
  • Another option for two devices in parallel is to use a single clock connected to the SYNC1 pins of both devices, with the SYNC2 pin of the primary device connected to VIN and the SYNC2 pin of the secondary device connected to GND.
  • For four devices in parallel, the SYNC1 pin of each device can be supplied with a separate clock, each phase shifted 90° with respect to the other. In this configuration, all SYNC2 pins should be connected to VIN. There is also an option where two clocks can be used, where the second clock is phase shifted 90° with respect to the first. In this instance, the table below details how the SYNC1 and SYNC2 pins of each device should be configured.
Figure 8-3 Parallel Configuration With External Sync
Table 8-2 Pin Connections for Four Parallel Devices Using External Sync and Two Clocks
DeviceSYNC1 PinSYNC2 Pin
1Clock 1VIN
2Clock 2VIN
3Clock 1GND
4Clock 2GND

The operation of multiple devices in parallel has an impact on some of the component calculations. For instance, since the enable pins are all connected together, the UVLO calculation as presented in the Enable and Adjust UVLO section will be modified according to the following equations, in which n is the number of paralleled devices:

Equation 34. GUID-DB7B72BD-86B0-4BD0-A92A-138E74B07CD5-low.gif
Equation 35. GUID-640C3BFF-D8F6-477C-983D-5310B4B94BC6-low.gif

Also, since all SS/TR pins will be connected for the paralleled devices, the soft-start calculation presented in the Soft-Start (SS/TR) section will be modified according to the following equation:

Equation 36. GUID-F0E78D4C-C506-4BBC-B146-4EB33B1BB3ED-low.gif

The compensation design is detailed in the Small Signal Model for Frequency Compensation section. The equation for R3 changes when the COMP pins of the devices in parallel are connected:

Equation 37. GUID-EA2F216C-36C1-4B7D-9A35-0BF11C254B7F-low.gif

Note that for parallel operation, the equations for the other compensation components, C1 and C2, will remain unchanged and still be calculated as shown in Equation 21 and Equation 22 due to the updated R3 calculation.