SLVSGF4C June   2022  – June 2026 TPS1641

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Shutdown Input (EN/SHDN)
      2. 7.3.2  Overvoltage Protection (OVP)
      3. 7.3.3  Output Slew Rate and Inrush Current Control (dVdt)
      4. 7.3.4  Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417
      5. 7.3.5  Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415
        1. 7.3.5.1 Internal Current Limit for the TPS16410 and TPS16411
      6. 7.3.6  Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads
      7. 7.3.7  Fast-Trip and Short-Circuit Protection
      8. 7.3.8  Analog Load Current Monitor (IMON) on the IOCP Pin
      9. 7.3.9  IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413)
      10. 7.3.10 Thermal Shutdown and Overtemperature Protection
      11. 7.3.11 Fault Response and Indication (FLT)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: 15W Power Limiting for Low Power Circuits (LPCs)
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting Overvoltage Setpoints
        2. 8.2.2.2 Setting the Output Overcurrent Setpoint (IOCP)
        3. 8.2.2.3 Setting the Output Power Limit
        4. 8.2.2.4 Monitoring the Output Current
        5. 8.2.2.5 Limiting the Inrush Current and Setting the Output Slew Rate
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter
    4. 8.4 Best Design Practices
    5. 8.5 Power Supply Recommendations
      1. 8.5.1 Transient Protection
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.6.1 Layout Guidelines

  • Verify that the high current-carrying power-path connections are as short as possible and are sized to carry at least twice the full-load current.
  • Tie the GND (PowerPAD) pin to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. Connect the device ground plane to the system power ground plane using a star connection.
  • The best placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Take care to minimize the loop area that the bypass-capacitor connection, the IN pin, and the GND pin of the IC form.
  • Locate the following support components close to the connection pins:
    • RILM or RPLM
    • RIOCP
    • CDLY
    • CdVdT
    • Resistors for OVP
  • Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing.
  • Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals.
  • Physically place protection devices such as TVS, snubbers, capacitors, or diodes close to the device the protection device is intended to protect. Route these protection devices with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1μF or greater between OUT and GND. These components must be physically close to the OUT pins. Take care to minimize the loop area that the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC form.