SLVSGZ9B February   2025  – July 2026 TPS4141-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Ratings
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Uni-directional Voltage Sensing
      2. 6.3.2 Bi-directional Voltage Sensing
      3. 6.3.3 Bi-directional and Uni-directional Voltage Sensing
      4. 6.3.4 High Voltage Input Range
      5. 6.3.5 Calculating the Output Voltage (VAOUT)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Divider Ratio Selection
        2. 7.2.2.2 Error Estimation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.1 Divider Ratio Selection

In this example, the HV input range is positive with respect to BAT-, so the TPS4141-Q1 is configured for uni-directional operation as Figure 7-2 shows.

Reference Figure 6-5 to determine the divider ratio. Select a divider ratio that maximizes the AOUT voltage range that is within the ADC full scale input range. With VREF = 0V (REF = HVGND), the lowest useable divider ratio is DIVNOM = 320V/V. Higher divider ratios are possible, but these reduce the AOUT voltage range with respect to the available ADC full scale input range.

Use DIV0 and DIV1 to select the nominal divider ratio. For applications that dynamically change the divider ratio in operation, control these pins by a general purpose I/O of the MCU. For static divider ratio settings, connect DIV0 and DIV1 to the supply or ground thereby saving MCU general purpose I/O for other purposes. For this design, the divider ratio is assumed static, so DIV0 connects to VDD and DIV1 connects to HVGND.

TPS4141-Q1 Uni-directional Measurement, DIVNOM = 320V/V Figure 7-2 Uni-directional Measurement, DIVNOM = 320V/V

If the application requires measuring both positive and negative HV voltages with respect to BAT-, configure the TPS4141-Q1 for bi-directional operation as shown in Figure 7-3. An external 2.048V (VREF) voltage reference is applied to REF which shifts the AOUT voltage to center around VREF. DIVNOM increases to 640V/V to support a HV input range from –1000V to 1000V.

TPS4141-Q1 Bi-directional Measurement, DIVNOM = 640V/V Figure 7-3 Bi-directional Measurement, DIVNOM = 640V/V