SLVSHA1C September   2024  – August 2025 TPS1685

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Logic Interface
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Protection
      2. 7.3.2  Insertion Delay
      3. 7.3.3  Overvoltage Protection
      4. 7.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 7.3.4.1.1 Start-Up Time Out
        2. 7.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 7.3.4.3 Active Current Limiting During Start-Up
        4. 7.3.4.4 Short-Circuit Protection
      5. 7.3.5  Analog Load Current Monitor (IMON)
      6. 7.3.6  Mode Selection (MODE)
      7. 7.3.7  Parallel Device Synchronization (SWEN)
      8. 7.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 7.3.8.1 Current Balancing During Start-Up
      9. 7.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Response and Indication (FLT)
      12. 7.3.12 Power Good Indication (PG)
      13. 7.3.13 Output Discharge
      14. 7.3.14 FET Health Monitoring
      15. 7.3.15 Single Point Failure Mitigation
        1. 7.3.15.1 IMON Pin Single Point Failure
        2. 7.3.15.2 IREF Pin Single Point Failure
        3. 7.3.15.3 ITIMER Pin Single Point Failure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Standalone Operation
      2. 8.1.2 Multiple Devices, Parallel Connection
    2. 8.2 Typical Application: 54V Power Path Protection in Data Center Servers
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Transient Protection
      2. 8.3.2 Output Short-Circuit Measurements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.1.2 Multiple Devices, Parallel Connection

TPS1685 Devices Connected in Parallel for Higher Current CapabilityFigure 8-2 Devices Connected in Parallel for Higher Current Capability

In this configuration, one TPS1685x device is designated as the primary device and controls the other TPS1685x devices in the chain which are designated as secondary devices. This configuration is achieved by connecting the primary device as follows:

  1. VDD is connected to IN through an R-C filter.
  2. MODE pin is left OPEN.
  3. ITIMER is connected through capacitor to GND.
  4. DVDT is connected through capacitor to GND.
  5. IREF is connected through resistor to GND.
  6. IMON is connected through resistor to GND.
  7. ILIM is connected through resistor to GND.
  8. SWEN is pulled up to a 3.3V to 5V standby rail. This rail must be powered up independent of the eFuse.

The secondary devices must be connected in the following manner:

  1. VDD is connected to IN through a R-C filter.
  2. MODE pin is connected to GND.
  3. ITIMER pin is left OPEN.
  4. ILIM is connected through resistor to GND.

The following pins of all devices must be connected together:

  1. IN
  2. OUT
  3. EN/UVLO
  4. OVP
  5. DVDT
  6. SWEN
  7. PG
  8. IMON
  9. IREF

In this configuration, all the devices are powered up and enabled simultaneously.

Power up: After power up or enable, all devices initially hold the SWEN low till the internal blocks are biased and initialized correctly. After that, each device releases a dedicated SWEN. After all devices have released the SWEN, the combined SWEN goes high and the devices are ready to turn on the respective FETs at the same time.

Inrush: During inrush, because the DVDT pins are tied together to a single DVDT capacitor all the devices turn on the output with the same slew rate (SR). Choose the common DVDT capacitor (CDVDT) as per the following Equation 14 and Equation 15.

Equation 14. S R V / m s = I I N R U S H A C L O A D m F
Equation 15. C D V D T n F = 48 S R V / m s

In this condition, the internal balancing circuit verifies that the load current is shared among all devices during start-up. This action prevents a situation where some devices turn on faster than others and experience more thermal stress as compared to other devices. This can potentially result in premature or partial shutdown of the parallel chain, or even SOA damage to the devices. The current balancing scheme provides the inrush capability of the chain scales according to the number of devices connected in parallel, thereby verifying successful start-up with larger output capacitances or higher loading during start-up.

All devices hold the respective PG signals low during start-up. After the output ramps up fully and reaches steady-state, each device releases a dedicated PG pulldown. Because the DVDT pins of all devices are tied together, the internal gate high detection of all devices is synchronized. There can be some threshold or timing mismatches between devices leading to PG assertion in a staggered manner. However, since the PG pins of all devices are tied together, the combined PG signal becomes high only after all devices have released the PG pulldown. This signal is sent to the downstream loads to allow power to be drawn.

Steady-state: During steady-state, all devices share current equally using the active current sharing mechanism which actively regulates the respective device RDSON to evenly distribute current across all the devices in the parallel chain.

Overcurrent during steady-state: The circuit-breaker threshold for the parallel chain is based on the total system current rather than the current flowing through individual devices. This is done by connecting the IMON pins of all the devices together. Similarly, the IREF pins of all devices are tied together and connected to a single RIREF (or an external VIREF source) to generate a common reference for the overcurrent protection block in all the devices. This action helps minimize the contribution of IIREF variation and RIREF tolerance to the overall mismatch in overcurrent threshold between devices. In this case, choose the combined RIMON as per the following Equation 16:

Equation 16. R I M O N = I I R E F × R I R E F G I M O N × I O C P T O T A L

The RILIM value for each individual eFuse must be selected based on the following Equation 17.

Equation 17. RILIM=1.1×N×RIMON3

Where N = number of devices in parallel chain.

Other variations:

The IREF pin can be driven from an external voltage reference (VIREF).

Equation 18. RIMON=VIREFGIMON×IOCPTOTAL

During an overcurrent event, the overcurrent detection of all the devices is triggered simultaneously. This in turn triggers the overcurrent blanking timer (ITIMER) on each device. However, only the primary device uses the ITIMER expiry event as a trigger to pull the SWEN low for all the devices, thereby initiating the circuit-breaker action for the whole chain. This mechanism verifies that the mismatches in the current distribution, overcurrent thresholds and ITIMER intervals among the devices do not degrade the accuracy of the circuit-breaker threshold of the complete parallel chain or the overcurrent blanking interval.

However, the secondary devices also start the backup overcurrent timer and can trigger the shutdown of the whole chain if the primary device fails to do so within a certain interval.

Severe overcurrent (short-circuit): If there is a severe fault at the output (for example, output shorted to ground with a low impedance path) during steady-state operation, the current builds up rapidly to a high value and triggers the fast-trip response in each device. The devices use two thresholds for fast-trip protection – a user-adjustable threshold ISFT as well as a fixed threshold IFFT . After the fast-trip, the devices enter into a latch-off fault condition till the device is power cycled or re-enabled or expires the auto-retry timer (only for auto-retry variants).