SLVSHI9B March   2025  – February 2026 TPS7H5020-SEP , TPS7H5020-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Tables
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage (VIN) and VLDO
      2. 7.3.2  Driver Input Voltage (PVIN)
      3. 7.3.3  Start-Up
      4. 7.3.4  Enable and Undervoltage Lockout (UVLO)
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Output Voltage Programming
      8. 7.3.8  Soft Start (SS)
      9. 7.3.9  Switching Frequency and External Synchronization
        1. 7.3.9.1 Internal Oscillator Mode
        2. 7.3.9.2 External Synchronization Mode
          1. 7.3.9.2.1 External Synchronization with TPS7H5021 and TPS7H5031
      10. 7.3.10 Duty Cycle Limit
      11. 7.3.11 Minimum On-Time and Off-Time
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Leading Edge Blank Time
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Gate Driver Output
      16. 7.3.16 Unpowered Voltage Clamp
      17. 7.3.17 Sourcing Driver Return (OUTH_REF)
      18. 7.3.18 Slope Compensation (RSC)
      19. 7.3.19 Frequency Compensation
      20. 7.3.20 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistor Selection
        3. 8.2.2.3  Driver PVIN Configuration
        4. 8.2.2.4  Soft-Start Capacitor Selection
        5. 8.2.2.5  Transformer Design
        6. 8.2.2.6  Primary Power Switch Selection
        7. 8.2.2.7  Output Diode Selection
        8. 8.2.2.8  RCD Clamp
        9. 8.2.2.9  Output Capacitance Selection
        10. 8.2.2.10 Current Sense Resistor
        11. 8.2.2.11 Frequency Compensation Component Selection
      3. 8.2.3 Application Curves
      4. 8.2.4 Boost Converter
      5. 8.2.5 Feedback Isolation Using ISOS510
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 TPS7H502x PWP Package
24-Pin HTSSOP With Thermal Pad
(Top View)
TPS7H5020-SP TPS7H5021-SP TPS7H5030-SP TPS7H5031-SP TPS7H5020-SEP TPS7H5021-SEP TPS7H5030-SEP TPS7H5031-SEP TPS7H503x PWP Package24-Pin HTSSOP With Thermal Pad(Top View)Figure 5-2 TPS7H503x PWP Package
24-Pin HTSSOP With Thermal Pad
(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME HTSSOP (TPS7H502x) HTSSOP (TPS7H503x)
AGND 16 16 — Ground. Return for the controller circuitry. Connect to PGND at printed circuit board level.
COMP 24 24 I/O Error amplifier output. The output is divided down by a factor CCSR and this scaled voltage is the input to the PWM comparator. Connect frequency compensation to this pin.
CS_ILIM 1 1 I Current sense for PWM control and cycle-by-cycle overcurrent protection. An input voltage over 1V on CS_ILIM triggers an overcurrent in the PWM controller. The sensed waveform on CS_ILIM contains a 150mV offset when compared to the COMP/CCSR voltage at the input of the PWM comparator.
EN 15 15 I Enable. Connecting the EN pin to a voltage greater than 0.6V enables the device. In addition, input undervoltage lockout (UVLO) can be adjusted by the user with a resistor divider from VIN to GND.
NC 12, 13 12, 13, 14 — No connect. This pin is not internally connected. These pins can be connected to GND to prevent charge buildup.
OUTH 2, 3 2, 3 O Driver stage source current output. Connect to the gate of the power transistor using a short, low-inductance path. A resistor between OUTH and the gate of the transistor can be used to adjust the turn-on speed.
OUTH_REF 11 11 O OUTH driver stage return. The voltage at OUTH_REF is nominally 6V less than the voltage present at PVIN. When the voltage at PVIN is 6V or greater, connect a 220nF capacitor between OUTH_REF and PVIN. This improves transient performance and minimizes potential radiation-induced single-event transients (SETs). For PVIN voltage less than 6V, connect OUTH_REF to PGND at the printed circuit board level. For TPS7H503x, a capacitor must always connected between OUTH_REF and PVIN since the minimum allowable PVIN voltage is 8V.
OUTL 4, 5 4, 5 O Driver stage sink current output. Connect to the gate of the power transistor using a short, low-inductance path. A resistor between OUTL and the gate of the transistor can be used to adjust the turn-off speed.
PGND 6, 7 6, 7 — Driver stage power ground. Connect to the source of the power transistor. Connect to AGND at the printed circuit board level.
PVIN 8, 9 8, 9 I Driver stage voltage input. The voltage range of PVIN is from 4.5V to 14V for TPS7H502x and 8V to 14V for TPS7H503x. The voltage being supplied to the gate of the power transistor is approximately equal to the input voltage at PVIN. This pin can be connected to VIN for single-supply operation. For the TPS7H502x devices, PVIN can also be connected to VLDO to provide a regulated gate drive voltage, between 4.5V and 5.5V, to the power transistor gate.
REFCAP 20 20 O 1.2V internal reference output. Requires a 470nF external capacitor to AGND. Do not load with external circuitry.
RSC 23 23 I/O Slope compensation programming for the controller. A resistor from RSC to AGND sets the desired slope compensation.
RT 19 19 I/O Switching frequency programming for controller. Connect a resistor from RT to GND to set the switching frequency of the controller. If an external clock input is used, the resistor still must be connected and selected to match the external clock frequency.
SS 21 21 I/O Soft start. An external capacitor connected to this pin sets the internal voltage reference rise time. Can be used for tracking and sequencing.
SYNC 18 18 I External clock input. For TPS7H502x, SYNC accepts a 100kHz to 1MHz external clock. SYNC accepts a clock with frequency from 100kHz to 500kHz for TPSH503x. Use a duty cycle between 40% and 60% for the external clock. The switching frequency of the controller outputs are the same as the external clock frequency. RT must be populated such that the frequency set by the resistor coincides with the external clock frequency. If external synchronization is not planned to be used, SYNC can either be tied directly to VLDO or to GND through a 10kΩ resistor.
THERMAL PAD — — — Thermal pad. Internally connected to AGND. Connect to one or more ground planes on the printed circuit board for improved thermal dissipation.
VIN 17 17 I Controller input voltage. The voltage range of VIN is from 4.5V to 14V for TPS7H502x and 8V to 14V for TPS7H503x. Powers internal control circuitry. Can be connected to PVIN for single-supply operation.
VLDO 10 10 O Output of internal regulator. For the TPS7H502x devices, this output is programmable and can be connected to PVIN for regulated GaN compatible driver voltage. In TPS7H502x, it is able to be programmed from 4.5V to 5.5V using a resistor divider than consists of a resistor from VLDO to VLDO_FB and another from VLDO_FB to AGND. These resistors must always be populated for proper operation. For TPS7H503x devices, this is a fixed 5V output. Requires at least 1μF external capacitor to AGND.
VLDO_FB 14 — I VLDO feedback pin for TPS7H502x. Used to program the VLDO output voltage. Nominally set to 1.2V using resistor divider from VLDO to AGND. The resistor divider must always be populated for proper operation.
VSENSE 22 22 I Inverting input of the error amplifier. Feedback pin that is nominally set to 0.6V using a resistor divider from the converter output.
(1) I = input, O = output, I/O = bidirectional