SLVSHL6C June   2025  – June 2026 TPSI2260-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 TI Reference Designs
    2. 9.2 Typical Application
      1. 9.2.1 Insulation Resistance Monitoring
      2. 9.2.2 Battery V- Reference Example
      3. 9.2.3 Chassis Ground Reference Example
      4. 9.2.4 Dielectric Withstand Testing (HiPot)
      5. 9.2.5 Design Requirements
      6. 9.2.6 Detailed Design Procedure - Chassis Ground Reference
        1. 9.2.6.1 RISO1 Selection
      7. 9.2.7 Application Performance Plot
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Component Placement
        2. 9.4.1.2 EMI Considerations
        3. 9.4.1.3 ESD Considerations
        4. 9.4.1.4 High-Voltage Considerations
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.4.2 Layout Example

Varying PCB implementations are possible depending on both the system EMI requirements and the system dielectric withstand testing (HiPot) parameters. The following figures detail a TPSI2260-Q1 layout example optimized for best EMI and ESD performance by implementing split resistance architecture on the secondary side.

An example 2-layer circuit layout using the TPSI2260-Q1 is shown below.

TPSI2260-Q1 TPSI2260-Q1 Example Layout - Top Layer Figure 9-10 TPSI2260-Q1 Example Layout - Top Layer
TPSI2260-Q1 TPSI2260-Q1 Example Layout - Bottom Layer Figure 9-11 TPSI2260-Q1 Example Layout - Bottom Layer