SLVSI74A July   2025  – November 2025 TLV61290

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 I2C Interface Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting
      2. 7.3.2 Switching frequency and Spread Spectrum Function
    4. 7.4 Device Functional Modes
      1. 7.4.1  Enable and Start-up
      2. 7.4.2  Operation Mode Setting
      3. 7.4.3  Bypass Mode
      4. 7.4.4  Boost Control Operation
      5. 7.4.5  Auto PFM Mode
      6. 7.4.6  Forced PWM Mode
      7. 7.4.7  Ultrasonic Mode
      8. 7.4.8  Output Discharge
      9. 7.4.9  Undervoltage Lockout
      10. 7.4.10 Current Limit Operation
      11. 7.4.11 Output Short-to-Ground Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Power-Good Indication Status
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Target Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multi-Read and Multi-Write
    6. 7.6 Register Maps
      1. 7.6.1 DeviceID Register
      2. 7.6.2 CONFIG Register
      3. 7.6.3 VOUTFLOORSET Register
      4. 7.6.4 ILIMBSTSET Register
      5. 7.6.5 VOUTROOFSET Register
      6. 7.6.6 STATUS Register
      7. 7.6.7 ILIMPTSET Register
      8. 7.6.8 BSTLOOP Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 TLV61290 with 2.5V-4.35V VIN, 3.4V VOUT, 4A Output Current
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detailed Design Parameters
          1. 8.2.1.2.1 Inductor Selection
          2. 8.2.1.2.2 Output Capacitor
          3. 8.2.1.2.3 Input Capacitor
          4. 8.2.1.2.4 Checking Loop Stability
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Information
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     79

7.4.3 Bypass Mode

The TLV61290 contains an internal switch for bypassing the dc/dc boost converter during bypass mode. When the input voltage is larger than the preset output voltage, the converter seamlessly transitions into 0% duty cycle operation and the bypass FET is fully turned on.

In auto PFM or Ultrasonic mode, entry in bypass mode is triggered by condition where VOUT >(1+1%)* VOUT_TAR and VIN > VOUT.

In forced PWM operation, the device enters into bypass mode from either of these two conditions:

  • VOUT >(1+2%)* VOUT_TAR.
  • Seven (7) consecutive cycle of maximum clamped off-time occurs ( typical tOFF is 2.25μs of each cycle and total 16μs).

Bypass mode exit is triggered when VOUT < VOUT_TAR-50mV.

In bypass mode operation, the load (2G RF PA for instance) is directly supplied from the battery for maximum RF output power, highest efficiency and lowest possible input-to-output voltage difference. The device consumes only a standby current of 30µA (typ). In bypass mode, the device is protected from short-circuit by a very fast current limit detection scheme.

During this operation, the output voltage follows the input voltage and does not fall below the programmed output voltage threshold as the input voltage decreases. The output voltage drop during bypass mode depends on the load current and input voltage, the resulting output voltage is calculated as:

Equation 4. V O U T = V I N - R D S O N ( B P ) × I O U T

Conversely, the efficiency in bypass mode is defined as:

Equation 5. η = 1 - R D S O N ( B P ) I O U T V I N
  • in which RDSON(BP) is the typical on-resistance of the bypass FET

During bypass mode, the TLV61290 device has overcurrent and short-circuit protection by a fast current limit detection scheme. If the current in the bypass FET exceeds approximately 10A (programmable via I2C), the bypass FET is turned off, then the TLV61290 enters into output short-to-ground protection mode. Once the overcurrent or short-circuit is released, the TLV61290 goes through the start-up procedure again.