SLVSI74A July   2025  – November 2025 TLV61290

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 I2C Interface Timing Characteristics
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting
      2. 7.3.2 Switching frequency and Spread Spectrum Function
    4. 7.4 Device Functional Modes
      1. 7.4.1  Enable and Start-up
      2. 7.4.2  Operation Mode Setting
      3. 7.4.3  Bypass Mode
      4. 7.4.4  Boost Control Operation
      5. 7.4.5  Auto PFM Mode
      6. 7.4.6  Forced PWM Mode
      7. 7.4.7  Ultrasonic Mode
      8. 7.4.8  Output Discharge
      9. 7.4.9  Undervoltage Lockout
      10. 7.4.10 Current Limit Operation
      11. 7.4.11 Output Short-to-Ground Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Power-Good Indication Status
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Target Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multi-Read and Multi-Write
    6. 7.6 Register Maps
      1. 7.6.1 DeviceID Register
      2. 7.6.2 CONFIG Register
      3. 7.6.3 VOUTFLOORSET Register
      4. 7.6.4 ILIMBSTSET Register
      5. 7.6.5 VOUTROOFSET Register
      6. 7.6.6 STATUS Register
      7. 7.6.7 ILIMPTSET Register
      8. 7.6.8 BSTLOOP Register
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 TLV61290 with 2.5V-4.35V VIN, 3.4V VOUT, 4A Output Current
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detailed Design Parameters
          1. 8.2.1.2.1 Inductor Selection
          2. 8.2.1.2.2 Output Capacitor
          3. 8.2.1.2.3 Input Capacitor
          4. 8.2.1.2.4 Checking Loop Stability
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Information
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     79

VOUTROOFSET Register

Memory location: 0x04

Table 7-9 VOUTROOFSET Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR/W0Reserved bit.
This bit is reserved for future use. During write operations data intended for this bit is ignored, and during read operations 0 is returned.
5:0VOUTROOF_THR/W0Output voltage threshold, dc/dc boost / bypass mode change.
R/W

0

R/W

1

000000: 2.85V
000001: 2.90V
000010: 2.95V
000011: 3.00V
000100: 3.05V
000101: 3.10V
000110: 3.15V
000111: 3.20V
001000: 3.25V
001001: 3.30V
001010: 3.35V
001011: 3.40V
001100: 3.45V
001101: 3.50V
001110: 3.55V
001111: 3.60V
010000: 3.65V
010001: 3.70V
010010: 3.75V
010011: 3.80V
010100: 3.85V
010101: 3.90V
010110: 3.95V
010111: 4.00V
011000: 4.05V
011001: 4.10V
011010: 4.15V
011011: 4.20V
011100: 4.25V
011101: 4.30V
011110: 4.35V
011111: 4.40V
100000: 4.45V
100001: 4.50V
100010: 4.55V
100011: 4.60V
100100: 4.65V
100101: 4.70V
100110: 4.75V
100111: 4.80V
101000: 4.85V
101001: 4.90V
101010: 4.95V
101011: 5.00V
110110: 2.80V
110111: 2.75V
111000: 2.70V
111001: 2.65V
111010: 2.60V
111011: 2.55V
111100: 2.50V
111101: 2.45V
111110: 2.40V
111111: 2.35V
101100 ~ 110101: Not Defined.
R/W1
R/W

1

R/W0